Effective Capacitance
J. Qian, S. Pullela and L.T. Pillage, Modeling the “Effective Capacitance” of RC Interconnect, IEEE Transactions on Computer-Aided Design, pp. 1526-1535, December 1994.
The Essence of AWE
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpL.T. Pillage and R.A. Rohrer, “The Essence of AWE”, Circuits and Devices Magazine, November 1994.
Metrics for RLC Transmission Line Termination
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpJohn Willis, Rohini Gupta and L.T. Pillage, “Metrics for RLC Transmission Line Termination”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, November 1994.
RC Interconnect Synthesis — A Moment Fitting Approach
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpN. Menezes, S. Pullela and L.T. Pillage, “RC Interconnect Synthesis — A Moment Fitting Approach”, Proceedings of the 1994 International Conference on Computer-Aided Design, Nov. 1994.
Domain Characterization of Transmission Line Models for Efficient Simulation
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpR. Gupta, S.Y. Kim and L.T. Pillage, “Domain Characterization of Transmission Line Models for Efficient Simulation”, Proceedings of the International Conference on Computer Design, October 1994.
Time-Domain Macromodels for VLSI Interconnect Analysis
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpS.Y. Kim, N. Gopal and L.T. Pillage, “Time-Domain Macromodels for VLSI Interconnect Analysis”, IEEE Transactions on Computer-Aided Design, pp. 1257-1270, October 1994.
OTTER: Optimal Termination of Transmission Lines Excluding Radiation
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpR. Gupta and L.T. Pillage, “OTTER: Optimal Termination of Transmission Lines Excluding Radiation”, Proceedings Design Automation Conference, June 1994.
A Gate Delay Model for High Performance CMOS
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpF. Dartu, N. Menezes, J. Qian and L.T. Pillage, “A Gate Delay Model for High Performance CMOS”, Proceedings Design Automation Conference, June 1994.
RICE: Rapid Interconnect Circuit Evaluation Using Asymptotic Waveform Evaluation
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpC. Ratzlaff and L.T. Pillage, “RICE: Rapid Interconnect Circuit Evaluation Using Asymptotic Waveform Evaluation”, IEEE Transactions on Computer-Aided Design, pp. 763-776, June 1994.
On the Stability of Moment- Matching Approximations in Asymptotic Waveform Evaluation
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpD.F. Anastaskis, N. Gopal, S.Y. Kim and L.T. Pillage, “On the Stability of Moment- Matching Approximations in Asymptotic Waveform Evaluation”, IEEE Transactions on Computer-Aided Design, pp. 729-736, June 1994.
Contact
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774