Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI

R.E. Bryant, K.T. Cheng, A.B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. Rabaey and A. Sangiovanni-Vincentelli, “Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI”, Proceedings of the IEEE, Special Issue on the Limits of Semiconductor Technology, pp. 341-366, March 2001.

Equipotential Shells for Efficient Inductance Extraction

M. Beattie, B. Krauter, L. Alatan and L. Pileggi, “Equipotential Shells for Efficient Inductance Extraction”, IEEE Transactions on Computer-Aided Design, Vol. 20, No. 1, January 2001.

Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations

E. Acar, S. Nassif and L. Pileggi, “Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations”, ACM/IEEE Workshop on Timing in the Specification and Synthesis of Digital Systems, December 2000.

Hierarchical Interconnect Circuit Models

M. Beattie, S. Gupta, L. Pileggi, “Hierarchical Interconnect Circuit Models”, Proceedings of the International Conference on Computer-Aided Design, November 2000.

Can We Continue to Predict Timing of ICs Prior to Manufacturing as Technologies Continue to Scale?

R. Arunachalam and L.T. Pileggi, “Can We Continue to Predict Timing of ICs Prior to Manufacturing as Technologies Continue to Scale?”, ISD Magazine, September 2000.

RC(L) Interconnect Sizing with Second Order Considerations

T. Lin and L. Pileggi, “RC(L) Interconnect Sizing with Second Order Considerations”, Proceedings of the SRC Techcon Conference, September 2000.

TACO: Timing Analysis with Coupling

R. Arunachalam, K. Rajagopal and L. Pileggi, “TACO: Timing Analysis with Coupling”, Proceedings of the Design Automation Conference, June 2000.

Impact of interconnect variations on the clock skew of a gigahertz microprocessor

Y. Liu, S. Nassif, L. Pileggi and A.J. Strojwas, “Impact of interconnect variations on the clock skew of a gigahertz microprocessor”, Proceedings of the Design Automation Conference, June 2000.

Electromagnetic Parasitic Extraction via a Multipole Method with Hierarchical Refinement

M. Beattie and L. Pileggi, “Electromagnetic Parasitic Extraction via a Multipole Method with Hierarchical Refinement”, Proceedings of the International Conference on Computer-Aided Design, November 1999.

Practical Considerations for Passive Reduction of RLC Circuits

A. Odabasioglu, M. Celik & L. T. Pileggi, “Practical Considerations for Passive Reduction of RLC Circuits”, Proceedings of the International Conference on Computer- Aided Design, November 1999.