Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses
H. Zhang, B. Krauter, M. Beattie and L. Pileggi, “Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses”, Design and Test in Europe Conference (DATE), March 2002.
Overcoming Wireload Model Uncertainty for Physical Design
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpP. Gopalakrishnan, A. Odabasioglu, L. T. Pileggi, and S. Raje, “Overcoming Wireload Model Uncertainty for Physical Design”, IEEE Transactions on Computer-Aided Design, Vol. 21, No. 1, January 2002.
Min/Max On-Chip Inductance Models and Delay Metrics
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpY-C. Lu, M. Celik, T. Young, and L. Pileggi, “Min/Max On-Chip Inductance Models and Delay Metrics”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
False coupling interactions in static timing analysis
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpR. Arunachalam, R. D. Blanton and L. Pileggi, “False coupling interactions in static timing analysis”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
Inductance 101 (Embedded Tutorial)
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpM. Beattie, L. Pileggi, “Inductance 101 (Embedded Tutorial)”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
Modeling Magnetic Coupling for Gigascale Interconnect
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpM. Beattie, L. Pileggi, “Modeling Magnetic Coupling for Gigascale Interconnect”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
Overcoming Wireload Model Uncertainty During Physical Design
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpP. Gopalakrishnan, A. Odabasioglu, L. Pileggi and S. Raje, “Overcoming Wireload Model Uncertainty During Physical Design”, Int’l Symposium on Physical Design (ISPD), April 2001.
RC(L)Interconnect Sizing With Second Order Considerations via Posynomial Programming
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpT. Lin and L. Pileggi, “RC(L)Interconnect Sizing With Second Order Considerations via Posynomial Programming”, Int’l Symposium on Physical Design (ISPD), April 2001.
ftd: Frequency to Time Domain Conversion for Reduced Order Interconnect Circuits
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpY. Liu, L. T. Pileggi and A.J. Strojwas, “ftd: Frequency to Time Domain Conversion for Reduced Order Interconnect Circuits”, IEEE Transactions on Circuits and Systems, April 2001.
Efficient Inductance Extraction via Windowing
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpM. Beattie and L. Pileggi, “Efficient Inductance Extraction via Windowing”, Design and Test in Europe Conference (DATE), March 2001.
Contact
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774