D. F. Anastasakis, N. Gopal, S.Y. Kim and L.T. Pillage, “On the Stability of Moment Matching Approximations in Asymptotic Waveform Evaluation”, Proceedings Design Automation Conference, June 1992.
C. Ratzlaff, S. Pullela and L.T. Pillage, “Effects of RC-Interconnect in a Hierarchical Timing Analyzer”, Proceedings Custom Integrated Circuits Conference, May 1992.
N. Gopal, E. Tuncer, D. Neikirk and L.T. Pillage, “Non-Uniform Models for Transmission Line Analysis”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, April, 1992.
N. Gopal, D. Neikirk and L.T. Pillage, “Evaluating RC Interconnect Using Moment Methods” Proceedings IEEE International Conference on Computer-Aided Design, November 1991.
N. Gopal, C. Ratzlaff, L.T. Pillage, “Constrained Approximation of Dominant Time Constants in RC Circuit Delay Models”, Proceedings of the International Mathematics and Computation Symposium, (Invited Paper), July 1991.
C. Ratzlaff, N. Gopal, L.T. Pillage, “RICE: Rapid Interconnect Circuit Evaluator”, Proceedings Design Automation Conference, (Best Paper Award Nomination), June 1991.
A. Balivada, D. Holberg and L.T. Pillage, “Calculation and Application of Time-Domain Sensitivities in Asymptotic Waveform Evaluation”, Proceedings Custom Integrated Circuits Conference, May 1991.
D. Holberg, S. Dutta and L.T. Pillage, “DC Parametrized Piecewise Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation”, Proceedings IEEE International Conference on Computer-Aided Design, November 1990.
S. Dutta and L.T. Pillage, “Calculating the Moments in AWE With Linear Complexity”, Proceedings of the SRC Techcon Conference, October 1990.
L.T. Pillage and S. Dutta, “A Path Tracing Algorithm for Asymptotic Waveform Evaluation of RLC Circuit Delay Models”, 1990 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, August 1990.
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