An Efficient Methodology for Extraction and Simulation of Transmission Lines for Application Specific Electronic Modules

S. Y. Kim, E. Tuncer, R. Gupta, B. Krauter, T.L. Savarino, D. P. Neikirk and L. T. Pillage, “An Efficient Methodology for Extraction and Simulation of Transmission Lines for Application Specific Electronic Modules”, Proceedings of the 1993 International Conference on Computer-Aided Design, Nov. 1993.

Efficient Circuit Model for Microstrip Lines Including Both Current Crowding and Skin Depth Effects

E. Tuncer, S.Y. Kim, L.T. Pillage and D. Neikirk, A New, “Efficient Circuit Model for Microstrip Lines Including Both Current Crowding and Skin Depth Effects”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, October 1993.

Evaluation by Parts of Mixed-Level dc- Connected Components in Logic Simulation

D.C. Yuan, L.T. Pillage, and J.T. Rahmeh, “Evaluation by Parts of Mixed-Level dc- Connected Components in Logic Simulation”, Proceedings Design Automation Conference, June 1993.

Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization

S. Pullela, N. Menezes and L.T. Pillage, “Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization”, Proceedings Design Automation Conference, June 1993.

Skew Reduction in Clock Trees Using Wire Width Optimization

N. Menezes, S. Pullela, A. Balivada and L.T. Pillage, “Skew Reduction in Clock Trees Using Wire Width Optimization”, Proceedings Custom Integrated Circuits Conference, May 1993.

AWE-Inspired

V. Raghavan, R.A. Rohrer, L.T. Pillage, J.Y. Lee, J.E. Braken, M.M. Alaybeyi, AWE-Inspired, “Proceedings Custom Integrated Circuits Conference”, (Invited Tutorial Paper), May 1993.

Finite-Pole Macromodels of Transmission Lines for Circuit Simulation

S.Y. Kim, N. Gopal and L.T. Pillage, “Finite-Pole Macromodels of Transmission Lines for Circuit Simulation”, Proceedings Custom Integrated Circuits Conference, May 1993.

ETA: Electrical-Level Timing Analysis

R. Brashear, D. Holberg, M.R. Mercer and L.T. Pillage, “ETA: Electrical-Level Timing Analysis”, Proceedings IEEE International Conference on Computer-Aided Design, November 1992.

AWE Macromodels for Incorporation in a Circuit Simulator

S.Y. Kim, N. Gopal and L.T. Pillage, “AWE Macromodels for Incorporation in a Circuit Simulator”, Proceedings IEEE International Conference on Computer-Aided Design, November 1992.

Introduction to Electrical and Computer Engineering

M. Becker, D. Beer, M.J. Gonzalez, C.M. Maziar, L.T. Pillage, M.D. Shermis, T.J. Wagner, G.L. Wise, “Introduction to Electrical and Computer Engineering”, Proceedings of the 1992 American Society on Engineering Education Annual Conference, November 1992