A Circuit-Theoretic Approach to State Estimation

/in , , /by

S. Li, A. Pandey, S. Kar, L. Pileggi, “A Circuit-Theoretic Approach to State Estimation,” IEEE PES Innovative Smart Grid Technologies Europe (ISGT-Europe), October 2020.

Sensitivity Analysis of Locked Circuits

/in , , /by

Sweeney, M. J. H. Heule, and L. Pileggi. “Sensitivity Analysis of Locked Circuits,” 23rd International Conference on Logic for Programming, Artificial Intelligence and Reasoning (LPAR-23), May 2020.

A LASSO-Inspired Approach for Localizing Power System Infeasibility

/in , , /by

S. Li, A. Pandey, and L. Pileggi, “A LASSO-Inspired Approach for Localizing Power System Infeasibility,” IEEE PES General Meeting, Montreal, Canada, August 2020.

Robust Event-Driven Dynamic Simulation using Power Flow

/in , , /by

A. Agrawal, A. Pandey, and L. Pileggi, Robust Event-Driven Dynamic Simulation using Power Flow, IEEE Power Systems Computation Conference (PSSC), June 2020.

Latch-Based Logic Locking

/in , , /by

J. Sweeney, M. Zackriya, S. Pagliarini, and L. Pileggi, “Latch-Based Logic Locking,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2020.

Latch-Based Logic Locking

/in , , /by

J. Sweeney, M. Zackriya, S. Pagliarini, and L. Pileggi, “Latch-Based Logic Locking,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 2020.

Logic IP for Low-Cost IC Design in Advanced CMOS Nodes

/in , , /by

M. Isgenc, M. Martins, S. Pagliarini and L. Pileggi, “Logic IP for Low-Cost IC Design in Advanced CMOS Nodes,” IEEE Transactions on Very Large Scale Integration, Vol 28, Issue 2, February 2020. (DOI:10.1109/TVLSI.2019.2942825.)

Steady-State Simulation for Combined Transmission and Distribution Systems

/in , , /by

A. Pandey and L. Pileggi, “Steady-State Simulation for Combined Transmission and Distribution Systems,” in IEEE Transactions on Smart Grid, August 2019. (DOI: 10.1109/TSG.2019.2932403)

From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration

/in , , /by

S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 39, Issue 2, February 2020. DOI (10.1109/TCAD.2018.2889772)

Efficient SpMV operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization

/in , , /by

F. Sadi , Joe Sweeney, T. M. Low, J. C. Hoe, L. Pileggi, F. Franchetti, “Efficient SpMV operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization,” IEEE/ACM International Symposium on Microarchitecture, October 2019.