A. Pandey, A. Agarwal, L. Pileggi, “Incremental Model Building Homotopy Approach for Solving Exact AC-Constrained Optimal Power Flow,” Hawaii International Conference on System Sciences-54, Hawaii, 2021.
X. He, S. Liu, S. Kargarrazi, V. Chen, M. Chamanzar, L. Pileggi, “A Multiplexed Active Digital Implantable Neural Probe,” In proceedings of SfN Global Connectome (virtual conference), January 11-13, 2021.
P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Hardware Redaction via Designer-Directed Fine-Grained Soft eFPGA Insertion,” In proceedings of Design and Test in Europe (DATE), February 1-5, 2021.
J. Sweeney, M.J.H. Heule, L. Pileggi, “Modeling Techniques for Logic Locking,” IEEE International Conference on Computer-Aided Design, November 2020.
S. Li, A. Pandey, S. Kar, L. Pileggi, “A Circuit-Theoretic Approach to State Estimation,” IEEE PES Innovative Smart Grid Technologies Europe (ISGT-Europe), October 2020.
Sweeney, M. J. H. Heule, and L. Pileggi. “Sensitivity Analysis of Locked Circuits,” 23rd International Conference on Logic for Programming, Artificial Intelligence and Reasoning (LPAR-23), May 2020.
S. Li, A. Pandey, and L. Pileggi, “A LASSO-Inspired Approach for Localizing Power System Infeasibility,” IEEE PES General Meeting, Montreal, Canada, August 2020.
A. Agrawal, A. Pandey, and L. Pileggi, Robust Event-Driven Dynamic Simulation using Power Flow, IEEE Power Systems Computation Conference (PSSC), June 2020.
J. Sweeney, M. Zackriya, S. Pagliarini, and L. Pileggi, “Latch-Based Logic Locking,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2020.
J. Sweeney, M. Zackriya, S. Pagliarini, and L. Pileggi, “Latch-Based Logic Locking,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 2020.
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774