S. Pullela, N. Menezes and L.T. Pileggi, “Moment-Sensitivity-Based Wire Sizing for Skew Reduction in On-Chip Clock Nets”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 2, pp. 210-215, February 1997.
Rohini Gupta, Bogdan Tutuianu and Lawrence Pileggi, “The Elmore Delay as a Bound for RC Trees with Generalized Input Signals”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 95-104, January 1997.
Rohini Gupta, Byron Krauter and Lawrence Pileggi, “Transmission Line Synthesis via Constrained Multivariable Optimization”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 6-19, January 1997.
F. Dartu and L.T. Pileggi, “Gate-level modeling of of coupling capacitance effects”, Proceedings of the SRC Techcon Conference, October 1996.
Florin Dartu, Bogdan Tutuianu and Lawrence T. Pileggi, “RC-Interconnect Macromodels for Timing Simulation”, Proceedings of the Design Automation Conference , 1996.
Florentin Dartu and Lawrence T. Pileggi, “Modeling Signal Waveshapes for Empirical CMOS Gate Delay Models”, Sixth International Workshop on Power and Timing Modeling, Optimization and Simulation, September 1996.
Rohini Gupta and Lawrence Pileggi, “Modeling Lossy Transmission lines Using the Method of Characteristics”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 43, No. 7, pp. 580-583, July 1996.
Rohini Gupta, John Willis and Lawrence T. Pileggi, “Low Power Design of Off-Chip Drivers and Transmission lines: A Branch and Bound Approach”, International Journal of High Speed Electronics and Systems, Vol. 7, no. 9, pp. 27-45, June 1996.
S. Pullela, N. Menezes and L.T. Pileggi, “Post-Processing of Clock Trees via Wiresizing and Buffering for Robust Design”, IEEE Transactions on Computer-Aided Design, pp. 691-701, June 1996.
Xun Yang, Byron Krauter and L. Pileggi, “Combined ac and Transient Power Distribution Analysis”, Proceedings of the Custom Integrated Circuits Conference, May 1996.
