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James C. Hoe is interested in many aspects of computer architecture and digital hardware design. His current research focuses on computer architecture, reconfigurable computing and high-level hardware design and synthesis. (Google Scholar Profile, select papers and student theses)

His current major research focus is on devising a new FPGA architecture for power efficient, high-performance computing. His research group is working on the CoRAM application development framework that (1) presents a virtualized FPGA execution environment and (2) offers a high-level programming abstraction to specify the control sequencing of kernel invocations and data movements. He is further developing an FPGA runtime environment that incorporates partial reconfiguration, virtualization, and protection features to manage an FPGA as a dynamically sharable multitasking compute resource.

Current Projects

Select Papers

  • CoRAM++: Supporting Data-Structure-Specific Memory Interfaces for FPGA Computing. Gabriel Weisz and James C. Hoe. Proc. International Conference on Field-programmable Logic and Applications (FPL), September 2015. (pdf | project)
  • Computer Generation of Hardware for Digital Signal Processing Transforms. Peter A. Milder, Franz Franchetti, James C. Hoe, and Markus Püschel. ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 17 Issue 2, April 2012. (acm | project)
  • CONNECT: Re-Examining Conventional Wisdom for Designing NoCs in the Context of FPGAs. Michael Papamichael and James C. Hoe. Proc. ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2012. (pdf | project)
  • Automatic Pipelining from Transactional Datapath Specifications. E. Nurvitadhi, J. C. Hoe, T. Kam, S. L. Lu. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Volume 30, Number 3,March 2011. (ieee | project)
  • CoRAM: An In-Fabric Memory Architecture for FPGA-based Computing. Eric S. Chung, James C. Hoe, and Kenneth Mai. Proc. ACM International Symposium on Field-Programmable Gate Arrays (FPGA), pp 97~106, February 2011. (pdf | project)
  • ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs. E. S. Chung, M. K. Papamichael, E. Nurvitadhi, J. C. Hoe, B. Falsafi and K. Mai. ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 2, Issue 2, June 2009. (acm | project)
  • Permuting Streaming Data Using RAMs. M. Pueschel, P. A. Milder and J. C. Hoe. Journal of the ACM (JACM), Volume 56, Issue 2, April 2009. (acm | project)
  • Reunion: Complexity-Effective Multicore Redundancy. J. C. Smolens, B. T. Gold, B. Falsafi, and J. C. Hoe. International Symposium on Microarchitecture (MICRO), December 2006.(pdf | project)
  • Statistical Sampling of Microarchitecture Simulation. Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, and James C. Hoe. ACM Transactions on Modeling and Computer Simulation, Volume 16, Number 3, June 2006. (acm | project)
  • Fingerprinting: Bounding Soft-Error Detection Latency and Bandwidth. J. C. Smolens, B. T. Gold, J. Kim, B. Falsafi, J. C. Hoe, and A. G. Nowatzyk. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2004. (pdf | project)
  • Operation-Centric Hardware Description and Synthesis. James C. Hoe and Arvind. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 23, Issue 9, September 2004. (ieee | project)
  • A Personal Supercomputer for Climate Research. James C. Hoe, Chris Hill and Alistair Adcroft. Supercomputing Conference (SC), November 1999. (pdf | project)
  • Network Interface for Message Passing Parallel Computation on a Workstation Cluster. James C. Hoe. Hot Interconnects II, August 1994. (pdf | project)
  • New Single Length Multiplication Semantic[sic] for The[sic] Next Generation 64-bit Processors. James Hoe and David Chiang. UCB CS252 Class Project Report, Fall 1991. (pdf)

Past Projects

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