CMU 18-447: Introduction to Computer Architecture

Course Schedule Spring 2009

www.ece.cmu.edu/~ece447

Blackboard

 

Reading assignments are to be completed BEFORE coming to class.  (P&H=The Hardware/Software

Interface, Fourth Edition by Patterson and Hennessy, Morgan Kaufmann/Elsvier.) You may also find it

helpful to preview lecture notes from Spring 2008 before class.  There will be additional assigned readings

from research papers.

 

Part 1: L1~L7 = Computer Basics

Part 2: L8~L15 = Processor Design

Part 3: L18~L23 = Memory System &

           L22 = I/O System &

           L23~L25 = Multicore and MP systems

 

 

Week

Date

 

 

Meetings

 

Readings

HW

Lab

 

1

1/12

L1

 

Introduction

 

P&H Ch1

 

 

 

 

 

1/14

L2

 

Computer Arithmetic: Adders

 

P&H Ch3

 

 

 

2

1/19

 

 

No classes (Martin Luther King, Jr. Day)

 

 

 

Lab1

 

 

1/21

LV

 

Verilog RTL Review in class

 

(Optional P&H App. C)

HW1

out

 

3

1/26

L3

 

Computer Arithmetic: Multipliers

 

P&H Ch3

 

 

 

1/28

L4

 

Floating Point

 

P&H Ch3

 

 

4

2/2

L5

 

ISA Design

 

P&H Ch2

(Optional P&H App. E)

HW1

due

HW2

out

Lab2

 

 

2/4

L6

 

MIPS ISA

 

P&H Ch2

(Optional P&H App. B)

 

 

5

2/9

L7

 

Performance and Cost

 

P&H Ch1.5 and 1.7

 

 

 

2/11

L8

 

Single-Cycle Implementation

 

P&H Ch4.1~4.4

 

HW2

due

 

6

2/16

 

 

Midterm 1: in class

 

 

 

Proj1

 

 

2/18

L9

 

Multi-Cycle Implementations

 

P&H Appendix D

 

 

 

7

2/23

L10

 

Pipelining: Basics

 

P&H Ch4.5~4.6

 

HW3

out

 

 

2/25

L11

 

Pipelining: Data Hazard and  Resolution

 

P&H Ch4.7

 

 

 

8

3/2

L12

 

Pipelining: Control Hazard and Resolution

 

P&H Ch4.8

 

 

Proj2

 

 

3/4

L13

 

Pipelining: Branch Prediction

 

P&H Ch4.8

 

HW3 due

 

 

3/6

 

 

Mid-Semester Break

 

 

 

 

 

3/9

 

 

No classes (Spring Break)

 

 

 

 

 

3/11

 

 

No classes (Spring Break)

 

 

 

 

9

3/16

L14

 

Pipelining: Exceptions

 

P&H Ch4.9

 

 

 

3/18

L15

 

Modern CPU Design

 

Rest of P&H Ch4

 

 

10

3/23

L16

 

Memory Technology and Organization

 

P&H Ch5

 

 

Proj3

 

 

3/25

L17

 

Caches

 

P&H Ch5.2~5.3

 

 

11

3/30

 

 

Midterm 2: in class

 

 

 

Proj4

 

 

4/1

L18

 

Multithreading and Multicore

+ Project 4 Kick-Off

 

 

 

 

12

4/6

L19

 

More caches

 

P&H Ch5.4~5.6

 

 

 

4/8

L20

 

VM: protection and paging

 

 

HW4 out

 

13

4/13

L21

 

VM: page tables and TLB

 

Rest of P&H Ch5

 

 

 

4/15

L22

 

VM: modern systems 

 

P&H Ch6

(Optional P&H Ch9)

 

 

 

4/16-18

 

 

Spring Carnival

 

 

 

 

14

4/20

L23

 

Cache Coherence

 

P&H Ch5.8

 

 

 

4/22

L24

 

Multicore Processors

 

 

HW4 due

 

15

4/27

L25

 

Busses

 

P&H Ch7

 

 

 

4/29

L26

 

I/O

 

 

 

 

 

5/7

 

 

Final Exam, Thursday, 5:30-8:30p.m,

BH 136A