Shimiao Li, Amritanshu Pandey, and Larry Pileggi. “Contingency Analysis with Warm Starter using Probabilistic Graphical Model.” Power Systems Computation Conference (PSCC), June 2024.
C. Talbot, Deepali Garg, L. Pileggi and K. Mai, “An IP-Agnostic Foundational Cell Array Offering Supply Chain Security,” The 61st Design Automation Conference, June 2024.
C. Talbot, Deepali Garg, L. Pileggi and K. Mai, “IP-Agnostic Standard Cell Fabric Offering Tamper Resistance and Supply Chain Resilience,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 2024.
D. Garg, J. Sweeney and L. Pileggi, Quantifying the Efficacy of Logic Locking Methods, International Conference on VLSI Design, Kolkata India, January 2024.
S. Li, J. Drgona, S. Abhyankar, L. Pileggi, Power Grid Behavioral Patterns and Risks of Generalization in Applied Machine Learning, 5th International Workshop on Applied Machine Learning for Intelligent Energy Systems (AMLIES 2023), Orlando FL, June 2023.
E. Foster, T. McNamara, A. Pandey and L. Pileggi, Actionable Three-Phase Infeasibility Optimization with Varying Slack Sources, IEEE PES General Meeting, July 16-20, 2023
B. Singer, A. Pandey, S. Li, L. Bauer, C. Miller, L. Pileggi, V. Sekar, Shedding Light on Inconsistencies in Grid Cybersecurity: Disconnects and Recommendations, IEEE Symposium on Security and Privacy, May 22-26, 2023.
P. Donti, A. Agarwal, L. Pileggi, Z. Kolter, Adversarially Robust Learning for Security-Constrained Optimal Power Flow, Neural Information Processing Systems, 2021
T. McNamara, A. Pandey, A. Agarwal, L. Pileggi, Two-Stage Homotopy Method to Incorporate Discrete Control Variables into AC-OPF, Power Systems Computation Conference (PSCC), June 27-July 1, 2022
A. Agarwal, P. Donti, L. Pileggi, Employing Adversarial Robustness Techniques for Large-Scale Stochastic Optimal Power Flow, 22nd Power Systems Computation Conference (PSCC), Porto, Portugal, 2022
A. Agarwal, L. Pileggi, Efficient Steady State Analysis of the Grid Using Electromagnetic Transient Models, 22nd Power Systems Computation Conference (PSCC), Porto, Portugal, 2022.
E. Foster, A. Pandey, L. Pileggi, Three-Phase Infeasibility Analysis for Distribution Grid Studies, Power Systems Computation Conference (PSCC), June 27-July 1, 2022.
A. Agarwal, A. Pandey and L. Pileggi, Fast AC Steady-State Power Grid Simulation and Optimization Using Prior Knowledge, (Best Paper Award) IEEE PES General Meeting, July 25-29, 2021.
S. (Cindy) Li, A. Pandey, and L. Pileggi, A WLAV-based Robust Hybrid State Estimation using Circuit-theoretic Approach, (Best Paper Session) IEEE PES General Meeting, July 25-29, 2021.
N. T. Bandele, A. Pandey and L. Pileggi, Analytical Inverter-Based Distributed Generator Model for Power Flow Analysis, IEEE PES General Meeting, July 25-29, 2021.
P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Top-Down Synthesis of Soft eFPGA Fabrics Using Standard ASIC Flows,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 29-April 1, 2021.
A. Pandey, A. Agarwal, L. Pileggi, “Incremental Model Building Homotopy Approach for Solving Exact AC-Constrained Optimal Power Flow,” Hawaii International Conference on System Sciences-54, Hawaii, 2021.
X. He, S. Liu, S. Kargarrazi, V. Chen, M. Chamanzar, L. Pileggi, “A Multiplexed Active Digital Implantable Neural Probe,” In proceedings of SfN Global Connectome (virtual conference), January 11-13, 2021.
P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Hardware Redaction via Designer-Directed Fine-Grained Soft eFPGA Insertion,” In proceedings of Design and Test in Europe (DATE), February 1-5, 2021.
J. Sweeney, M.J.H. Heule, L. Pileggi, “Modeling Techniques for Logic Locking,” IEEE International Conference on Computer-Aided Design, November 2020.
S. Li, A. Pandey, S. Kar, L. Pileggi, “A Circuit-Theoretic Approach to State Estimation,” IEEE PES Innovative Smart Grid Technologies Europe (ISGT-Europe), October 2020.
Sweeney, M. J. H. Heule, and L. Pileggi. “Sensitivity Analysis of Locked Circuits,” 23rd International Conference on Logic for Programming, Artificial Intelligence and Reasoning (LPAR-23), May 2020.
S. Li, A. Pandey, and L. Pileggi, “A LASSO-Inspired Approach for Localizing Power System Infeasibility,” IEEE PES General Meeting, Montreal, Canada, August 2020.
A. Agrawal, A. Pandey, and L. Pileggi, Robust Event-Driven Dynamic Simulation using Power Flow, IEEE Power Systems Computation Conference (PSSC), June 2020.
J. Sweeney, M. Zackriya, S. Pagliarini, and L. Pileggi, “Latch-Based Logic Locking,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2020.
J. Sweeney, M. Zackriya, S. Pagliarini, and L. Pileggi, “Latch-Based Logic Locking,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 2020.
M. Isgenc, M. Martins, S. Pagliarini and L. Pileggi, “Logic IP for Low-Cost IC Design in Advanced CMOS Nodes,” IEEE Transactions on Very Large Scale Integration, Vol 28, Issue 2, February 2020. (DOI:10.1109/TVLSI.2019.2942825.)
A. Pandey and L. Pileggi, “Steady-State Simulation for Combined Transmission and Distribution Systems,” in IEEE Transactions on Smart Grid, August 2019. (DOI: 10.1109/TSG.2019.2932403)
S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 39, Issue 2, February 2020. DOI (10.1109/TCAD.2018.2889772)
F. Sadi , Joe Sweeney, T. M. Low, J. C. Hoe, L. Pileggi, F. Franchetti, “Efficient SpMV operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization,” IEEE/ACM International Symposium on Microarchitecture, October 2019.
A. Jovicic, M. Jereminov, L. Pileggi, G. Hug, “A Linear Formulation for Power System State Estimation including RTU and PMU Measurements,” IEEE PES Innovative Smart Grid Technologies Europe Conference, 2019.
A. Pandey, A. Agarwal, M. Jereminov, M.R. Wagner, D.M. Bromberg, L. Pileggi, “Robust Sequential Steady-State Analysis of Cascading Outages,” IEEE PES Innovative Smart Grid Technologies Europe Conference, 2019.
A. Agarwal, A. Pandey, M. Jereminov, L. Pileggi, “Implicitly Modeling Frequency Control with Power Flow,” IEEE PES Innovative Smart Grid Technologies Europe Conference, 2019.
A. Pandey, A. Agarwal, M. Jereminov, B. Rawn, T. Nwachuku and L. Pileggi, “Improving Voltage Profile of the Nigerian Power Grid,” in Proc. IEEE PES/IAS PowerAfrica Conference, Abuja Nigeria, August 2019.
M. Jereminov, A. Terzakis, M. Wagner, A. Pandey, L. Pileggi, “Robust and Efficient Power Flow Convergence with G-min Stepping Homotopy Method,” in Proc. IEEE Conference on Environment, Electrical Engineering and I&CPS Europe, Genoa, Italy, June 2019.
M. R. Wagner, M. Jereminov, A. Pandey, and L. Pileggi, “A Probabilistic Approach to Power System State Estimation using a Linear Algorithm,” in 2019 IEEE Conference on Environment and Electrical Engineering and I&CPS Europe, 2019.
M. Jereminov, A. Jovicic, M. Wagner, G. Hug, L. Pileggi, “Equivalent Circuit Programming for Estimating the State of a Power System,” in Proc. IEEE PowerTech Milan, June 2019.
M. R. Wagner, M. Jereminov, A. Pandey, and L. Pileggi, “A Probabilistic Approach to Power System State Estimation using a Linear Algorithm,” in 2019 IEEE Conference on Environment and Electrical Engineering and I&CPS Europe, 2019.
S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, December 2018.
M. Jereminov, B. Hooi, A. Pandey, H. Song, C. Faloutsos and L. Pileggi, “Impact of Load Models on Power Flow Optimization,” IEEE PES General Meeting, Atlanta, GA, August 2019.
J. Sweeney, M. Zackriya, S. Pagliarini and L. Pileggi, Securing Digital Systems via Split-Chip Obfuscation, GOMACTech Technical Program, March 2019.
B. Hooi, D. Eswaran, A. Pandey, M. Jereminov, L. Pileggi, and C. Faloutsos, “ChangeDAR: Online Localized Change Detection for Sensor Data on a Graph,” (Best Student Paper Award, Runner Up), Proceedings of the 2018 ACM Conference on Information and Knowledge Management, 2018.
T. Jackson, S. Pagliarini and L. Pileggi, “An Oscillatory Neural Network with Programmable Resistive Synapses,” in 28 nm CMOS, IEEE International Conference on Rebooting Computing, November 2018.
A. Jovicic, M. Jeremino, L. Pileggi and G. Hug, “An Equivalent Circuit Formulation for Power System State Estimation including PMUs,” (Best Paper Award, Second Prize), 50th North American Power Symposium, October 2018.
B. Hooi, D. Eswaran, H.A. Song, A. Pandey, M. Jereminov, L. Pileggi, and C. Faloutsos. “GridWatch: Sensor Placement and Anomaly Detection in the Electrical Grid,” European Conference on Machine Learning and Principles and Practice of Knowledge Discovery in Databases (ECML-PKDD) 2018.
S. Liu, T. Rabuske, L. Pileggi, J. Fernandez, J. Paramesh, “A 125 Ms/S 10.4 ENOB 10.1 fJ/conv-Step Multi-Comparator SAR ADC with Comparator Noise Scaling in 65nm CMOS,” IEEE European Solid-State Circuits conference, September 2018.
M.R. Wagner, A. Pandey, M. Jereminov, and L. Pileggi. Robust Probabilistic Analysis of Transmission Power Systems based on Equivalent Circuit Formulation, Proceedings of the International Conference on Probabilistic Methods Applied to Power Systems, June 2018.
Sadi, F., Sweeney, J., McMillan, S., Low, T. M., Hoe, J., Pileggi, L., & Franchetti, F., “PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV”. HPEC: High Performance Embedded Computing Annual Workshop(2018).
A. Pandey, M. Jereminov, M. Wagner, G. Hug, and L. Pileggi, “Robust Convergence of Power Flow using Tx Stepping Method with Equivalent Circuit Formulation, Power Systems Computation Conference”, June 2018.
B. Hooi, H.A. Song, A. Pandey, M. Jereminov, L. Pileggi, and Christos Faloutsos. StreamCast: Fast and Online Mining of Power Grid Time Sequences. Proceedings of the 2018 SIAM.
H.A. Song, B. Hooi, A. Pandey, M. Jereminov, L. Pileggi, C. Faloutsos, “PowerCast: Mining and Forecasting Power Grid Sequences”, ECML-PKDD 2017 Conference, September 2017.
E. Calayir, J. Xu, L. Pileggi, G. K. Fedder, N. Singh, S. Merugu and G. Piazza, “Self-healing Narrowband Filters via 3D Heterogeneous Integration of AlN MEMS and CMOS chips”, 2017 IEEE International Ultrasonics Symposium (IUS), Washington, D.C., September 2017.
S. Bhuin, J. Sweeney, S. Pagliarini, A. K. Biswas, L. Pileggi, “A Self-Calibrating Sense Amplifier for A True Random Number Generator Using Hybrid FinFET-Straintronic MTJ”, IEEE International Symposium on Nanoscale Architectures (NANOARCH), July 2017.
T. C. Jackson and L. Pileggi, “A Mixed-Signal Oscillatory Neural Network Architecture for Integration with Resistive Crossbar Memory Arrays”, TECHCON 2017, Austin, Texas.
S. Bhuin and L. Pileggi, “A Self-Calibrating Sense Amplifier for a True Random Number Generator Using Strained MTJ”, TECHCON 2017, Austin, Texas.
M. Jereminov, A. Pandey, H.A. Song, B. Hooi, C. Faloutsos, L. Pileggi, “Linear Load Model for Robust Power System Analysis”, IEEE PES Integrative Smart Grid Technologies Europe, September 2017.
S. Bhuin, A. Biswas, L.Pileggi, “Strained MTJs with Latch-based Sensing for Stochastic Computing”, IEEE International Conference on Nanotechnology, July 2017.
J. Xu, G. Piazza, L. Pileggi and G. K. Fedder, “Reconfigurable AlN resonator filter design based on extended statistical element selection” 2017 Transducers – 2017 19th International Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS),Kaohsiung, June 2017.
A. Pandey, M. Jereminov, G. Hug, and L. Pileggi, “Improving Power Flow Robustness via Circuit Simulation Methods”, IEEE PES General Meeting, (Prize Paper Award), July 2017.
S. Pagliarini, M. Martins, L. Pileggi, “Virtual Characterization for Exhaustive DFM Evaluation of Logic Cell Libraries”, 18th International Symposium on Quality Electronic Design (ISQED), March 2017.
M. Isgenc, S. Pagliarini, L. Pileggi, “Evaluating the Benefits of a Relaxed BEOL Pitch for Deeply Scaled ICs”, 18th International Symposium on Quality Electronic Design (ISQED), March 2017.
M. Isgenc, M. Martins, S. Pagliarini, L. Pileggi, “Exhaustive DFM evaluation of logic cell libraries via virtual characterization, IEEE/ACM Workshop on Variability Modeling and Characterization”, November 2016.
A. Pandey, M. Jereminov, X. Li, G. Hug, L. Pileggi, “Aggregated Load and Generation Equivalent Circuit Models with Semi-Empirical Data Fitting”, IEEE Green Energy and Systems Conference (IGESC 2016), November 2016.
M. Jereminov, A. Pandey, G. Hug, X. Li and L. Pileggi, “Steady-State Analysis of Power System Harmonics Using Equivalent Split-Circuit Models”, IEEE PES Integrative Smart Grid Technologies Europe, October 2016.
A. Pandey, M. Jereminov, G. Hug, X. Li and L. Pileggi, “Unified Power System Analyses and Models using Equivalent Circuit Formulation”, IEEE PES Innovative Smart Grid Technologies Conference, September 2016.
R. Carley, G. Colak, L. Chomas, L. Pileggi and K. Mai, “Technologies for Secure RFID Authentication of Medicinal Pills and Capsules”, IEEE International Conference on RFID Technology and Applications (RFID-TA), September 2016.
R. Shi, T. Jackson, B. Swenson, S. Kar and L. Pileggi, “On the Design of Phase Locked Loop Oscillatory Neural Networks: Mitigation of Transmission Delay Effects”, International Joint Conference on Neural Networks, July 2016.
R. Liu, J. Weldon and L. Pileggi, “Extended Statistical Element Selection: A Calibration Method for High Resolution in Analog/RF Designs”, Design Automation Conference (DAC 2016), June 2016.
M. Jereminov, D. Bromberg, X. Li, G. Hug and L. Pileggi, “Improving Robustness and Modeling Generality for Power Flow Analysis” IEEE PES Transmission and Distribution Conference, Dallas, Texas, May 2016.
M. Jereminov, D. Bromberg, A. Pandey, G. Hug, X. Li and L. Pileggi, “An Equivalent Circuit Formulation for Three-Phase Power Flow Analysis of Distribution Systems” IEEE PES Transmission and Distribution Conference, Dallas, Texas, May 2016.
Q. Guo, T.-M. Low, N. Alachiotis, B. Akin, L. Pileggi, J.C. Hoe, F. Franchetti, “Enabling Portable Energy Efficiency with Memory Accelerated Library”, 48th Annual IEEE/ACM International Symposium on Microarchitecture, 2015.
F. Wang, S. Yin, M. Jun, X. Li, T. Mukherjee, R. Negi, L. Pileggi, “Re-thinking Polynomial Optimization: Efficient Programming of Reconfigurable Radio Frequency (RF) Systems by Convexification”, Asia and South Pacific Design Automation Conference, January 2016.
X. Chen, D. Bromberg, G. Hug, X. Li and L. Pileggi, ” A Robust and Efficient Power Series Method for Tracing PV Curves”, The 47th North American Power Symposium, October 2015.
T. C. Jackson, A. A. Sharma, R. Shi, J. Weldon, and L. Pileggi, “Using TMO-based RRAM Multi-Level Cells and Nano-Oscillators for Efficient ONN Implementation”,TECHCON 2015, Austin, Texas.
A. Sharma, T. Jackson, J. Bain, L. Pileggi and J. Weldon, “High Performance, Integrated 1T1R Oxide-based Oscillator: Stack Engineering for Low-Power Operation in Neural Network Applications”,in IEEE Symp. VLSI Technology, June 2015.
H.E. Sumbul, K. Vaidyanathan, Q. Zhu, F. Franchetti, L. Pileggi, “Application-Specific Synthesis of Embedded Logic-in-Memory Designs”, manuscript accepted for publishing in Design Automation Conference (DAC 2015), June 2015.
E. Calayir, J. Xu, A. Patterson, G. K. Fedder, G. Piazza, L. Pileggi, “3D Integration of AlN MEMS Filters and CMOS for Self-Healing RF Front-Ends”,Government Microcircuit Applications and Critical Technology Conference, March 2015.
D. Bromberg, G. Hug, X. Li and L. Pileggi, “An Equivalent Circuit Formulation of the Power Flow Problem with Current and Voltage State Variables”,Powertech Eindhoven, June 2015.
T. C. Jackson, A. A. Sharma, J. A. Bain, J. A. Weldon, and L. Pileggi, “An RRAM-Based Oscillatory Neural Network”,in Proc. 2015 Latin American Symposium on Circuits and Systems. Montevideo, Uruguay, 2015.
Q. Guo, N. Alachiotis, B. Akin, F. Sadi, G. Xu, T.M. Low, L. Pileggi, J.C. Hoe, and F. Franchetti, “3D-Stacked Memory-Side Acceleration: Accelerator and System Design”, WoNDP: 2nd Int’l Workshop on Near-Data Processing, December 2014.
V. Calayir, M.Darwish, J. Weldon and L. Pileggi, “Analog Neuromorphic Computing Enabled by Multi-Gate Programmable Resistive Devices, Design and Test in Europe” (DATE), March 2015.
Y.-C. Wang, S. Yin, M. Jun, X. Li, L. Pileggi, T. Mukherjee, R. Negi, “Accurate Passivity-Enforced Macromodeling for RF Circuits via Iterative Zero/Pole Update Based on Measurement Data”, 20th Asia and South Pacific Design Automation Conference (ASP-DAC), 2015.
M. Jun, R. Negi, Y.-C. Wang, T. Mukherjee, X. Li, J. Tao, and L. Pileggi, “Joint Invariant Estimation of RF impairments for Reconfigurable Radio Frequency(RF) Front-end”, Globecom Workshop – Emerging Technologies for 5G Wireless Cellular Networks, 2014.
D. Bromberg, M. Moneck, V. Sokalski, L. Pileggi, J-G. Zhu, “Experimental Demonstration of Four-Terminal Magnetic Logic Device with Separate Read- and Write-Paths, International Electron Devices Meeting”, December 2014.
D.M. Bromberg, E. Sumbul, J-G. Zhu and L. Pileggi, “All-Magnetic MRAM Based on Four Terminal mCell Device”, 13th Joint MMM/Intermag Conference, November 2014.
Minhee Jun, Jun Tao, Ying-Chih Wang, Shihui Yin, Rohit Negi, Xin Li, Tamal Mukherjee and Lawrence Pileggi, “Environment-adaptable efficient optimization for programming of reconfigurable radio frequency (RF) receivers”, IEEE Military Communications Conference (MILCOM), 2014.
F. Sadi, B. Akin, D. Popovici, J. Hoe, L. Pileggi, F. Franchetti, “Algorithm/Hardware Co-optimized SAR Image Reconstruction with 3D-stacked Logic in Memory”, Eighteenth Annual High Performance Embedded Computing (HPEC) Workshop at MIT Lincoln Laboratory, September 2014.
R. Liu, L. Pileggi and J. Weldon, “A Wideband RF Receiver with >80 dB Harmonic Rejection Ratio”, Int’l Custom Integrated Circuits Conference, September 2014.
K. Vaidyanathan, L. Liebmann, A. Strojwas, L. Pileggi, “Sub-20 nm Design Technology Co-Optimization for Standard Cell Logic”, Int’l Conference on Computer-Aided Design, November 2014.
T. Jackson, V. Calayir and L. Pileggi, “Integrating Emerging Devices and CMOS for Efficient Cellular Neural Networks”, Proceedings of the SRC Techcon Conference, September 2014.
K. Vaidyanathan, R. Liu, E. Sumbul, Q. Zhu, F. Franchetti, L. Pileggi, “Efficient and Secure Intellectual Property (IP) Design with Split Fabrication”, Hardware-Oriented Security and Trust, May 2014.
K. Vaidyanathan, B. P. Das, E. Sumbul, R. Liu, L. Pileggi, “Building Trusted ICs using Split Fabrication”, Hardware-Oriented Security and Trust, May 2014.
K. Vaidyanathan, B. Prasad Das, L. Pileggi, “Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack”, IEEE/ACM Design Automation Conference, June 2014.
M. T. Moneck, V. Sokalski, D. M. Bromberg, J. Wu, Z. Dai, L. Pileggi, J.-G. Zhu, “Fabrication Challenges in Developing All-Metal Magnetic Logic Circuits”, 2014 International Magnetics Conference.
J.-G. Zhu, D. Bromberg, V. Sokalski, M.T. Moneck, J. Wu, Z. Dai, L. Pileggi, “mLogic: All Spin Logic Device and Circuits for Future Electronics”, IEEE Transactions on Magnetics, INTERMAG 2014.
V. H-C. Chen and L. Pileggi, “A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI”, International Solid State Circuits Conference (ISSCC), February 2014.
J. Tao, Y.-C. Wang, M. Jun, X. Li, R. Negi, T. Mukherjee, L. Pileggi, “Toward Efficient Programming of Reconfigurable Radio Frequency (RF) Receivers”, 19th Asia and South Pacific Design Automation Conference (ASP-DAC), January 2014.
Qiuling Zhu, Berkin Akin, H. Ekin Sumbul, James C. Hoe, Larry Pileggi, Franz Franchetti, “A 3D-Stacked Logic-in-Memory Accelerator for Application-Specific Data Intensive Computing”, IEEE International 3D Systems Integration Conference, October 2013.
S. Sun, F. Wang, S. Yaldiz, X. Li, L. Pileggi, A. Natarajan, M. Ferriss, J. Plouchart, B. Sadhu, B. Parker, A. Valdes-Garcia, M. Sanduleanu, J. Tierno, D. Friedman, “Indirect Performance Sensing for On-Chip Analog Self-Healing via Bayesian Model Fusion”, Int’l Custom Integrated Circuits Conference, September 2013.
Qiuling Zhu, Tobias Graf, H. Ekin Sumbul, Larry Pileggi, Franz Franchetti, “A Logic-in-Memory Accelerated 3D-DRAM for Sparse Matrix-Matrix Multiplication”, Seventeenth Annual High Performance Embedded Computing (HPEC) Workshop at MIT Lincoln Laboratory (Best Paper Award), September 2013.
V. Calayir and L. Pileggi, “All-Magnetic Analog Associative Memory”, International NEWCAS Conference, June 2013.
V. Calayir, T. Jackson, A. Tazzoli, G. Piazza and L. Pileggi, “Neurocomputing and Associative Memories Based on Ovenized Aluminum Nitride Resonators”, International Joint Conference on Neural Networks, August 2013.
V. Calayir and L. Pileggi, “Fully-Digital Oscillatory Associative Memories Enabled by Non-volatile Logic”, International Joint Conference on Neural Networks, August 2013.
V. H.-C. Chen and L. Pileggi, “An 8.5mW 5GS/s 6b Flash ADC with Dynamic Offset Calibration in 32nm CMOS SOI”, in IEEE Symp. VLSI Circuits, June 2013.
J. Tao, Y-C. Wang, M. Jun, X. Li, R. Negi, T. Mukherjee and L. Pileggi, “Efficient System-Level Performance Modeling and Optimization for Reprogrammable Radio Frequency (RF) Systems”, Frontiers in Analog CAD Workshop, February 2013.
E. Sumbul, A. Patterson, G. Fedder, F. Franchetti, G. Piazza and L. Pileggi, “Trusted Split-Fabrication System-on-Chip Design Technology and Methodology”, (Invited Paper) GOMACTech Technical Program, March 2013.
K. Vaidyanathan, L. Liebmann and L. Pileggi, “Rethinking ASIC design with next-generation lithography and process integration”, SPIE Advanced Lithography Conference, February 2013.
V. Sokalski, D.M. Bromberg, D. Morris, M.T. Moneck, E. Yang, L. Pileggi, J-G. Zhu, “Naturally Oxidized FeCo as a Magnetic Coupling Layer for Electrically Isolated Read/Write Paths in mLogic”, 12th Joint MMM/Intermag Conference, January 2013.
D. Bromberg, D. Morris, L. Pileggi and J. Zhu, “All-Magnetic, Nonvolatile, Addressable Chainlink Memory”, 12th Joint MMM/Intermag Conference, January 2013.
Q. Zhu, L. Pileggi and F. Franchetti, Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography, Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October 2012.
J.-O. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakani, S. Yaldiz, L. Pileggi, R. Harjani, S. Reynolds, J. A. Tierno, D. Friedman, “A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS”, Int’l Custom Integrated Circuits Conference, Sept. 2012.
Q. Zhu, L. Pileggi and F. Franchetti, “Smart Memory Synthesis for Energy-Efficient Computed Tomography Reconstruction”, Proceedings of the SRC Techcon Conference, September 2012.
Q. Zhu, K. Vaidyanathan, O. Shacham, M. Horowitz, L. Pileggi and F. Franchetti, “Design Automation Framework for Application-Specific Logic-in-Memory Blocks”, IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2012.
B. Sadhu, M.A. Ferriss, J-O. Plouchart, A.S. Natarajan, A.V. Rylyakov, A. Valdes-Garcia, B.D. Parker, S. Reynolds, A. Babakhani, S. Yaldiz, L. Pileggi, R. Harjani, J. Tierno and D. Friedman, “A 21.8-27.5GHz PLL in 32nm SOI Using Gm Linearization to Achieve -130dBc/Hz Phase Noise at 10MHz Offset from a 22GHz Carrier”, 2012 Radio Frequency Integrated Circuits Symposium, June 2012.
D. Morris, D. Bromberg, J. Zhu and L. Pileggi, “Magnetic Logic Circuits with Minimal Connections to CMOS”, IEEE CAS-FEST, 2012.
D. Morris, D. Bromberg, J. Zhu and L. Pileggi, “mLogic: Ultra-Low Voltage Non-Volatile Logic Circuits Using STT-MTJ Devices”, IEEE/ACM Design Automation Conference (DAC), 2012.
D. Morris, D. Bromberg, J. Zhu, and L. Pileggi, “Spintronic Circuits and Devices for Low-Voltage Electronics”, (Invited Paper) In Proceedings of WOFE, 2011.
Q. Zhu, L. Pileggi , F. Franchetti, “Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography”, VLSI-SoC, October 2012.
F. Wang, G. Keskin, A. Phelps, J. Rotner, X. Li, G. Fedder, T. Mukherjee and L. Pileggi, “Statistical Design and Optimization for Adaptive Post-Silicon Tuning of MEMS Filters”, IEEE/ACM Design Automation Conference (DAC), 2012.
D. Bromberg, D. Morris, L. Pileggi and J. Zhu, “Novel STT-MTJ device enabling all-metallic logic circuits”, International Magnetics Conference, May 2012.
K. Vaidyanathan, S.H. NG, D. Morris, N. Lafferty, L. Liebmann, W. Huang, K. Lai, L. Pileggi, A.J. Strojwas, “Design and Manufacturability Tradeoffs in Unidirectional & Bidirectional Standard Cell Images in 14 nm”, SPIE Advanced Lithography Conference, February 2012.
W. Huang, D. Morris, N. Lafferty, L. Liebmann, K. Vaidyanathan, K. Lai, L. Pileggi, A.J. Strojwas, “Local Loops for Robust Inter-Layer Routing at Sub-20 nm Nodes”, SPIE Advanced Lithography Conference, February 2012.
L. Pileggi, “Center for Circuit and System Solutions (C2S2): Accomplishments and Future Challenges”, (Invited Paper) GOMACTech Technical Program, March 2012.
Q. Zhu, C.R. Berger, E. Turner, L. Pileggi, F. Franchetti, “Polar Format Synthetic Aperture RADAR in Energy Efficient Application-Specific Logic-in-Memory”, IEEE International Conference on Acoustics, Speech and Signal Processing, Kyoto Japan, March 2012.
D. Morris, D. Bromberg, J. Zhu, and L. Pileggi, “mLogic: Ultra-Low Voltage Logic Circuits with Non-Volatile Spintronic Devices”, (Invited Paper) Workshop on Frontier Electronics, December 2011.
J. Zhu, D. Bromberg, D. Morris and L. Pileggi, “Novel STT Device Design To Enable All Metallic Spin Logic Circuits Free of Transistors”, (Invited Presentation) Conference on Magnetism and Magnetic Materials, October 2011.
M. Althoff, A. Rajhans, B. Krogh, S. Yaldiz, X. Li and L. Pileggi, “Formal Verification of Phase-Locked Loops Using Reachability Analysis and Continuization”, Int’l Conference on Computer-Aided Design (Best Paper Award), November 2011.
Qiuling Zhu, Franz Franchetti and Larry Pileggi, “Application-Specific Logic-in-Memory for Polar Format Synthetic Aperture Radar”, Fifteenth Annual High Performance Embedded Computing (HPEC) Workshop at MIT Lincoln Laboratory, September 2011.
S. Yaldiz, V. Calayir, X. Li, L. Pileggi, et al, “Indirect Phase Noise Sensing for Self-Healing Voltage Controlled Oscillators”, Int’l Custom Integrated Circuits Conference, Sept. 2011.
C.-Y. Wen, J. Paramesh, L. T. Pileggi, J. Li, S. Kim, J. Proesel, C. Lam, “Post-Silicon Calibration of Analog CMOS Using Phase-Change Memory Cells”, European Solid-State Device Research Conference (ESSDERC), September 2011.
M. Althoff, A. Rajhans, B.H. Krogh, S. Yaldiz, X. Li, L. Pileggi, “Using Continuization in Reachability Analysis for the Verification of a Phase-Locked Loop”, In Proc. Frontiers in Analog Circuit (FAC) Synthesis and Verification, July 2011.
D. Morris, K. Vaidyanathan and L. Pileggi, “Design Without Rules: A Pattern Construct Methodology”, Proceedings of the SRC Techcon Conference, September 2011.
D. Morris, K. Vaidyanathan, N. Lafferty, K. Lai, L. Liebmann, L. Pileggi, “Design of Embedded Memory and Logic Based On Pattern Constructs”, IEEE Symposium on VLSI (Invited Presentation), June 2011.
C.-Y. Wen, J. Li, S. Kim, M. Breitwisch, C. Lam, J. Paramesh, L. T. Pileggi, “A Non-volatile Look-Up Table Design Using PCM (Phase-Change Memory) Cells”, IEEE Symposium on VLSI, June 2011.
S. Yaldiz, F. Wang, X. Li, L. Pileggi, A.S. Natarajan, M.A. Ferriss, J. Tierno, “Virtual Phase Noise Sensor for Self-Healing Voltage Controlled Oscillators”, GOMACTech-11 Technical Program, March 2011.
V. Rovner, T. Jhaveri, Daniel Morris, Andrzej J. Strojwas, and Larry Pileggi, “Performance and Manufacturability Trade-offs of Pattern Minimization for sub-22nm Technology Nodes”, SPIE Advanced Lithography Conference, February 2011.
C.-Y. Wen, E. K. Chua, R. Zhao, T. C. Chong, J. A. Bain, T. E. Schlesinger, L. T. Pileggi, J. Paramesh, “A Phase-change via-Reconfigurable On-Chip Inductor”, International Electron Devices Meeting, December 2010.
G. Keskin, J. Proesel and L. Pileggi, “Statistical Modeling and Post Manufacturing Configuration for Scaled Analog CMOS”, Int’l Custom Integrated Circuits Conference, Sept. 2010.
J. Proesel, G. Keskin, J.O. Plouchart and L. Pileggi, “An 8-bit 1.5GS/s Flash ADC Using Post-Manufacturing Statistical Selection”, Int’l Custom Integrated Circuits Conference, Sept. 2010.
A. Bonnoit, S. Herbert and L. Pileggi, “Reducing Variability in Chip-Multiprocessors with Adaptive Body Biasing”, International Symposium on Low Power Electronics and Design, August 2010.
G. Keskin, J. Proesel and L. Pileggi, “Modeling of Statistical Element Selection Based Self-Healing Analog Circuits”, Proceedings of the SRC Techcon Conference, September 2010.
D. Morris, S. Rovner, L. Pileggi, A. Strojwas and K. Vaidyanathan, “Enabling Application-Specific Integrated Circuits on Limited Pattern Constructs”, IEEE Symposium on VLSI (Invited Presentation), June 2010.
L. Liebmann, J. Hibbeler, N. Hieter, L. Pileggi, M. Moe, T. Jhaveri, V. Rovner, “Demonstrating the benefits of template-based design-technology co-optimization”, SPIE Advanced Lithography Conference, February 2010.
T. Jhaveri, U. Urslan, V. Rovner, L. Pileggi & A. J. Strojwas, “Application of the Cost-Per-Good-Die Metric for Process-Design Co-optimization”, SPIE Advanced Lithography Conference, Selected for Keynote Presentation, February 2010.
A. Bonnoit, S. Herbert, L. Pileggi and D. Marculescu, “Integrating Dynamic Voltage/Frequency Scaling and Adaptive Body Biasing using Test-time Voltage Selection”, International Symposium on Low Power Electronics and Design, August 2009.
J. Proesel, G. Keskin and L. Pileggi, “An 8-bit Flash ADC using Statistical Element Selection”, Proceedings of the SRC Techcon Conference, September 2009.
U. Arslan, J. Wang and L. Pileggi, “An SRAM Design Framework for Deeply-Scaled CMOS”, Proceedings of the SRC Techcon Conference, September 2009.
B. Taylor, D. Morris and L. Pileggi, “Fixed Depth Reasoning in Satisfiability and its Applications to Combinatorial Optimization”, Proceedings of the SRC Techcon Conference, September 2009.
T. Jhaveri, A. J. Strojwas, L. Pileggi and V. Rovner, “Economic Assessment of Lithography Strategies for the 22nm Technology Node”, Proceedings of the SPIE/BACUS Symposium on Photomask Technology, September 2009.
A. J. Strojwas, T. Jhaveri, V. Rovner and L. Pileggi, “Creating an Affordable 22nm Node using Design-Lithography Co-Optimization”, Proceedings of ACM/IEEE Design Automation Conference, June 2009.
J. Wang, S. Yaldiz, X. Li and L. Pileggi, “SRAM Parametric Failure Analysis, Proceedings of ACM/IEEE Design Automation Conference”, June 2009.
S. Yaldiz, U. Arslan, X. Li and L. Pileggi, “Efficient Statistical Analysis of Read Timing Failures in SRAM Circuits”, IEEE Int’l Symposium on Quality in Electronic Design, March 2009.
Lars Liebmann, Larry Pileggi, Jason Hibbeler, Vyacheslav Rovner, Tejas Jhaveri, Greg Northrop, “Simplify to Survive: Prescriptive Layouts Ensure Profitable Scaling to 32nm and Beyond”, SPIE Advanced Lithography Conference, February 2009.
Tejas Jhaveri, Andrzej Strojwas, Larry Pileggi & Vyacheslav Rovner, “OPC Simplification & Mask Cost Reduction using Regular Design Fabrics”, SPIE Advanced Lithography Conference, February 2009.
Bin Wan, Jian Wang, Gokce Keskin, and Lawrence T. Pileggi, “Ring Oscillators for Single Process-Parameter Monitoring”, IEEE Workshop on Test Structure Design for Variability Characterization, November 2008.
J. Proesel and L. Pileggi, ‘A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS’, Int’l Custom Integrated Circuits Conference, Sept. 2008.
U. Arslan, M. McCartney, M. Bhargava, X. Li, K. Mai and L. Pileggi, “Variation-Tolerant SRAM Sense-Amplifier Timing Using Configurable Replica Bitlines”, Int’l Custom Integrated Circuits Conference, Sept. 2008.
L. Pileggi, G. Keskin, X. Li, K. Mai and J. Proesel, “Mismatch Analysis and Statistical Design at 65 nm and Below”, Invited Paper, Int’l Custom Integrated Circuits Conference, Sept. 2008.
U. Arslan, M. McCartney, M. Bhargava, L. Pileggi and K. Mai, “Variation-Tolerant SRAM Sense-Amp Timing using Configurable Replica Bitlines”, Proceedings of the SRC Techcon Conference, September 2008.
J. Proesel and L. Pileggi, “A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS”, Proceedings of the SRC Techcon Conference, September 2008.
G. Keskin, L. Pileggi, X. Li and K. Mai, “Process Variation Effects on Input Offset Voltage of CMOS SRAM Sense Amplifiers”, Proceedings of the SRC Techcon Conference, September 2008.
E. Small, S.M. Sadeghipour, L. Pileggi, M. Asheghi, “Thermal Analyses of Confined Cell Design for Phase Change Random Access Memory (PCRAM)”, ITherm, May 2008.
T. Jhaveri, A.J. Strojwas, L. Pileggi, V. Rovner, “Enabling Technology Scaling with ‘In Production’ Lithography Processes”, SPIE Advanced Lithography Conference, February 2008.
J. Brown, B. Taylor, R. D. Blanton, and L. Pileggi, “Automated Testability Enhancements for Logic Brick Libraries”, Proceedings of Design and Test Europe, March 2008.
B. Taylor and L. Pileggi, “Exact Methods for Physical Design of Regular Logic Bricks”, Proceedings of the SRC Techcon Conference, October 2007.
X. Li, B. Taylor, Y-T. Chen and L. Pileggi, “Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization” , Proceedings of the International Conference on Computer-Aided Design, November 2007.
K. Yu, S. Wang, A. Gerdemann, C. Weldon, D. Reber, J. Vasek, S. Veeraraghavan, V. Rovner, T. Jhaveri, T. Hersan, L. Pileggi”,Regular Layout Performance Dependence on Cell Abutment”, Joint Conference on Design For Manufacturing, June 2007.
J. Wang, X. Li and L. Pileggi, “Parameterized Macromodeling for Analog System-Level Design Exploration”, Proceedings of ACM/IEEE Design Automation Conference, June 2007.
B.Taylor and L. Pileggi, “Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks”, Proceedings of ACM/IEEE Design Automation Conference, June 2007.
X. Li and L. Pileggi, “Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits”, Proceedings of ACM/IEEE Design Automation Conference, June 2007.
K.Y. Tong, V. Rovner, L. Pileggi and V. Kheterpal, “Design Methodology of Regular Logic Bricks for Robust Integrated Circuits”, Int’l Conference on Computer Design, October 2006.
G. Keskin, X. Li and L. Pileggi, “Active On-Die Suppression of Power Supply Noise”, Int’l Custom Integrated Circuits Conference, Sept. 2006.
P. Gopalakrishnan, X. Li and L. Pileggi, “A Metric-Embedding Inspired Approach to Timing-driven FPGA Placement”, Design Automation Conference, June 2006.
X. Li, J. Le and L. Pileggi, “Projection-Based Statistical Analysis of Full-Chip Leakage Power with Non-Log-Normal Distributions”, Design Automation Conference, June 2006.
T. Jhaveri, L. Pileggi, V. Rovner, A.J. Strojwas, “Maximization of layout printability/manufacturability by extreme layout regularity”, SPIE 31st International Symposium on Microlithography Symposium (invited presentation), February 2006.
L. Pileggi and A.J. Strojwas, “Regular Fabrics for Nano-Scaled CMOS Technologies”, International Solid State Circuits Conference (invited presentation), February 2006.
X. Li, J. Le, L. Pileggi and A.J. Strojwas, “Projection-Based Performance Modeling for Inter/Intra-Die Variations”, Proceedings of the International Conference on Computer-Aided Design, November 2005.
X. Li, J. Le, M. Celik and L. Pileggi, “Defining Statistical Sensitivity for Timing Optimization of Logic Circuits with Large-Scale Process and Environmental Variations”, Proceedings of the International Conference on Computer-Aided Design, November 2005.
X. Li, P. Li and L. Pileggi, “Parameterized Interconnect Order Reduction with Explicit-and-Implicit Multi-Parameter Moment Matching for Inter/Intra-Die Variations”, Proceedings of the International Conference on Computer-Aided Design, November 2005.
X. Li, J. Wang, W. Chiang and L. Pileggi, “Performance-Centering Optimization for System-Level Analog Design Exploration”, Proceedings of the International Conference on Computer-Aided Design, November 2005.
P. Li, Y. Dong and L. Pileggi, “Temperature-Dependent Optimization of Cache Leakage Power Dissipation”, Proceedings of the International Conference on Computer Design, October 2005.
R. Batra, P. Li, L. Pileggi, W.J. Chiang, “A Behavioral Level Approach for Nonlinear Dynamic Modeling of Voltage-Controlled Oscillators”, Int’l Custom Integrated Circuits Conference, Sept. 2005.
G. Keskin, X. Li and L. Pileggi, “Reducing Power Supply Noise in Integrated Circuits Using Active Resistors”, Proceedings of the SRC Techcon Conference, October 2005.
P. Gopalakrishnan and L. Pileggi, “Timing Driven Initial Placement for FPGAs via Graph Matching”, Proceedings of the SRC Techcon Conference, October 2005.
Y. Xu, K. L. Hsiung, L. Pileggi, and S. Boyd, “OPERA: OPtimization with Ellipsoidal uncertainty for Robust Analog IC design”, Design Automation Conference, June 2005.
Y. Zhan, X. Li, A. Strojwas, and L. Pileggi, “Correlation-Aware Statistical Timing Analysis with Non-Gaussian Delay Distributions”, Design Automation Conference, June 2005.
V. Kheterpal, T. Hersan, V. Rovner, D. Motiani, Y. Takagawa, L. Pileggi and A. Strojwas, “Design Methodology for IC Manufacturability Based on Regular Logic-Bricks”, Design Automation Conference, June 2005.
Y. Xu and L. Pileggi, “Metal-mask Configurable RF Integrated Circuits”, GOMACTech-05 Technical Program, April 2005.
X. Li, K.Y. Tong, Y. Xu and L. Pileggi, “Robust Optimization for Radiation Hardened Analog/RF Circuits”, GOMACTech-05 Technical Program, April 2005.
P. Li and L. Pileggi, “Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction”, Design and Test in Europe Conference (DATE), February 2005.
S. Biswas, P. Li, S. Blanton and L. Pileggi, “Specification Test Compaction for Analog Circuits and MEMS”, Design and Test in Europe Conference (DATE), February 2005.
R. Batra, P. Li, Y-T. Chen and L. Pileggi, “A Methodology for Analog Circuit Macromodeling”, IEEE International Workshop on Behavioral Modeling and Simulation, October 2004.
R. Marculescu, D. Marculescu and L. Pileggi, “Toward an Integrated Design Methodology Fault Tolerant”, Multiple Clock/Voltage Integrated Systems, Proceedings of the International Conference on Computer Design, October 2004.
V. Chandra, H. Schmit and L. Pileggi, “A Power Aware System Level Interconnect Design Methodology for Latency-Insensitive”, Proceedings of the International Conference on Computer-Aided Design, November 2004.
P. Li, L. Pileggi, M. Ashegi, R. Chandra, “Efficient Full-Chip Thermal Modeling and Analysis”, Proceedings of the International Conference on Computer-Aided Design, November 2004.
P. Li and L. Pileggi, “Efficient Harmonic Balance Simulation Using Multi-Level Frequency Decomposition”, Proceedings of the International Conference on Computer-Aided Design, November 2004.
X. Li and L. Pileggi, “Robust Analog/RF Circuit Design with Projection-Based Posynomial”, Proceedings of the International Conference on Computer-Aided Design, November 2004.
X. Li, J. Le, P. Gopalakrishnan and L. Pileggi, “Asymptotic Probability Extraction for Non-Normal Distributions of Circuit Performance”, Proceedings of the International Conference on Computer-Aided Design (Best Paper Award), November 2004.
Y. Xu, C. Boone and L. Pileggi, “Metal-mask configurable RF Front-end Circuits”, in Proceedings of IEEE RFIC Symposium, June 2004.
Satrajit Gupta and Larry Pileggi, “Hierarchical Modeling of Magnetic Coupling”, ACM/IEEE Design Automation Conference, June 2004.
Veerbhan Kheterpal, Andrzej Strojwas, Larry Pileggi, “Routing Architecture Exploration for Regular Fabrics”, ACM/IEEE Design Automation Conference, June 2004.
Jiayong Le, Xin Li and Larry Pileggi, “STAC: Statistical Timing Analysis with Correlation”, ACM/IEEE Design Automation Conference, June 2004.
Yang Xu, Larry Pileggi, Stephan Boyd, “ORACLE: Optimization with Recourse of Analog Circuits including Layout Extration”, ACM/IEEE Design Automation Conference, June 2004.
Xin Li, Yang Xu, Peng Li, Padmini Gopalakrishnan and Lawrence Pileggi, “A Frequency Relaxation Approach for Analog/RF System-Level Simulation”, ACM/IEEE Design Automation Conference, June 2004.
L. Pileggi and A.J. Strojwas, Exploring Regular Fabrics to Optimize the Performance-Cost Trade-Off, International Solid State Circuits Conference (invited presentation), February 2004.
A. Koorapaty, V. Kheterapal, M. Fu, P. Gopalakrishnan and L. Pileggi, “Exploring Logic Block Granularity for Regular Fabrics”, Design and Test in Europe Conference (DATE), February 2004.
V. Chandra, A. Xu, H. Schmit and L. Pileggi, “An Interconnect Channel Design Methodology for High Performance Integrated Circuits”, Design and Test in Europe Conference (DATE), February 2004.
P. Li and L. Pileggi, “Modeling Nonlinear Communication ICs Using a Multivariate Formulation”, IEEE International Workshop on Behavioral Modeling and Simulation, October 2003.
P. Li, X. Li, Y. Xu and L. Pileggi, “A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits”, Proceedings of the International Conference on Computer-Aided Design, November 2003.
J. Le, A. Devgan and L. Pileggi, “Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics”, Proceedings of the International Conference on Computer-Aided Design, November 2003.
H. Zheng, B. Krauter, L. Pileggi, “On-Package Decoupling Optimization with Package Macromodels”, Int’l Custom Integrated Circuits Conference, Sept. 2003.
K.Y. Tong, V. Kheterapal, S. Rovner, H. Schmit, L. Pileggi, R. Puri, “Regular Logic Fabrics for a Via Patterned Gate Array (VPGA)”, Int’l Custom Integrated Circuits Conference, Sept. 2003.
A. Koorapaty, L. Pileggi, H. Schmit, “Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics”, International Conference on Field Programmable Logic and Applications, September 2003.
S. Gupta and L. Pileggi, “Hierarchical Modeling of Electrostatic and Magnetostatic Coupling”, Proceedings of the SRC Techcon Conference, August 2003.
X. Qi, G. Leonhardt, D. Flees, X-D, Yang, S. Kim, S. Mueller, H. Mau and L. Pileggi, “Simulation Approach for Inductance Effects of VLSI Interconnects”, In Proc. of the Great Lakes Symposium on VLSI, May 2003.
D. Pandini, L. Pileggi, A. Strojwas, “Bounding the Efforts on Congestion Optimization for Physical Synthesis”, In Proc. of the Great Lakes Symposium on VLSI, May 2003.
I. Bolsens, A. Broom, C. Hamlin, P. Magarshack, Z. Or-Bach and L. Pileggi, Fast, “Cheap and Under Control: The Next Implementation Fabric”, IEEE/ACM Design Automation Conference, June 2003.
L. Pileggi, H. Schmit, A.J. Strojwas, et al, “Exploring Regular Fabrics to Optimize the Performance-Cost Trade-Off”, IEEE/ACM Design Automation Conference, June 2003.
X. Li, P. Li, Y. Xu and L. Pileggi, “Analog and RF Circuits Macromodels for System-Level Analysis”, IEEE/ACM Design Automation Conference, June 2003.
P. Li and L. Pileggi, “NORM: Compact Model Order Reduction of Weakly Nonlinear Systems”, IEEE/ACM Design Automation Conference (Best Paper Award), June 2003.
C. Patel, A. Cozzie, H. Schmit and L. Pileggi, “An Architecture Exploration of Via Patterned Gate Arrays”, Internation Symposium on Physical Design, April 2003.
E. Malley, A. Salinas, K. Ismail and L. Pileggi, “Power Comparison of Throughput Optimized IC Busses”, IEEE Symposium on VLSI, February 2003.
A. Koorapaty, V. Chandra, K.Y. Tong, C. Patel, L. Pileggi and H. Schmit, “Heterogeneous Programmable Logic Block Architectures”, Design and Test in Europe Conference (DATE), March 2003.
Y. Xu and L. Pileggi, “Noise Macromodel for Radio Frequency Integrated Circuits”, Design and Test in Europe Conference (DATE), March 2003.
X. Li and L. Pileggi, “A Frequency Separation Macromodel for System-Level Simulation of RF Circuits”, Asia-Pacific Design Automation Conference, February 2003.
P. Li and L. Pileggi, “Nonlinear Distortion Analysis Via Linear-Centric Models”, Asia- Pacific Design Automation Conference, February 2003.
M. Celik, H. Zheng and L. Pileggi, “Efficient Reduction of Susceptance-Based Package Models Using PRIMA”, Proceedings of the Topical Meeting on Electrical Performance of Electronic Packaging, October 2002.
H. Zheng and L. Pileggi, “Robust and Passive Model OrderReduction for Circuits Containing Susceptance Elements”, Proceedings of the International Conference on Computer-Aided Design, November 2002.
T. Lin and L. Pileggi, “Throughput Driven IC Communication Synthesis”, Proceedings of the International Conference on Computer-Aided Design, November 2002.
A. Koorapaty and L. Pileggi, Modular, “Fabric-specific Synthesis for Programmable Architectures”, International Conference on Field Programmable Logic and Applications, September 2002, France.
T. Lin, M. Beattie and L. Pileggi, “On the Efficacy of Simplified 2D On-Chip Inductance Models”, ACM/IEEE Design Automation Conference, June 2002.
H. Zheng and L. Pileggi, “Modeling and Analysis of Regular Symmetrically Structured Power/Ground Distribution Networks”, ACM/IEEE Design Automation Conference, June 2002.
D. Pandini, L. Pileggi and A. Strojwas, “Understanding and Addressing the Impact of Wiring Congestion During Technology Mapping”, Int’l Symposium on Physical Design (ISPD), April 2002.
D. Pandini, L. Pileggi and A. Strojwas, “Congestion-Aware Logic Synthesis”, Design and Test in Europe Conference (DATE), March 2002.
P. Li and L. Pileggi, “A Linear-Centric Modeling Approach to Harmonic Balance Analysis”, Design and Test in Europe Conference (DATE), March 2002.
T. Lin, M. Beattie and L. Pileggi, “On-Chip Inductance Models:3D or not 3D?”, Design and Test in Europe Conference (DATE), March 2002.
E. Acar, L. Pileggi and S. Nassif, “A Linear-Centric Simulation Framework for Parametric Fluctuations”, Design and Test in Europe Conference (DATE), March 2002.
H. Zhang, B. Krauter, M. Beattie and L. Pileggi, “Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses”, Design and Test in Europe Conference (DATE), March 2002.
E. Acar, S. Nassif and L. Pileggi, “Time-Domain Simulation of Variational Interconnect Models”, Int’l Symposium on Quality in Electronic Design, March 2002.
Y-C. Lu, M. Celik, T. Young, and L. Pileggi, “Min/Max On-Chip Inductance Models and Delay Metrics”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
R. Arunachalam, R. D. Blanton and L. Pileggi, “False coupling interactions in static timing analysis”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
M. Beattie, L. Pileggi, “Inductance 101 (Embedded Tutorial)”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
M. Beattie, L. Pileggi, “Modeling Magnetic Coupling for Gigascale Interconnect”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
P. Gopalakrishnan, A. Odabasioglu, L. Pileggi and S. Raje, “Overcoming Wireload Model Uncertainty During Physical Design”, Int’l Symposium on Physical Design (ISPD), April 2001.
T. Lin and L. Pileggi, “RC(L)Interconnect Sizing With Second Order Considerations via Posynomial Programming”, Int’l Symposium on Physical Design (ISPD), April 2001.
M. Beattie and L. Pileggi, “Efficient Inductance Extraction via Windowing”, Design and Test in Europe Conference (DATE), March 2001.
E. Acar, S. Nassif and L. Pileggi, Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations, Int’l Symposium on Quality in Electronic Design, March 2001.
E. Acar, S. Nassif and L. Pileggi, “Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations”, ACM/IEEE Workshop on Timing in the Specification and Synthesis of Digital Systems, December 2000.
M. Beattie, S. Gupta, L. Pileggi, “Hierarchical Interconnect Circuit Models”, Proceedings of the International Conference on Computer-Aided Design, November 2000.
R. Arunachalam and L.T. Pileggi, “Can We Continue to Predict Timing of ICs Prior to Manufacturing as Technologies Continue to Scale?”, ISD Magazine, September 2000.
T. Lin and L. Pileggi, “RC(L) Interconnect Sizing with Second Order Considerations”, Proceedings of the SRC Techcon Conference, September 2000.
R. Arunachalam, K. Rajagopal and L. Pileggi, “TACO: Timing Analysis with Coupling”, Proceedings of the Design Automation Conference, June 2000.
Y. Liu, S. Nassif, L. Pileggi and A.J. Strojwas, “Impact of interconnect variations on the clock skew of a gigahertz microprocessor”, Proceedings of the Design Automation Conference, June 2000.
M. Beattie and L. Pileggi, “Electromagnetic Parasitic Extraction via a Multipole Method with Hierarchical Refinement”, Proceedings of the International Conference on Computer-Aided Design, November 1999.
A. Odabasioglu, M. Celik & L. T. Pileggi, “Practical Considerations for Passive Reduction of RLC Circuits”, Proceedings of the International Conference on Computer- Aided Design, November 1999.
A. Odabasioglu, M. Celik & L. T. Pileggi, “Efficient and Accurate Delay Metrics for RC Interconnect”, PATMOS: International Workshop on Power and Timing Modeling, Optimization and Simulation, October 1999.
Y. Liu, L. Pileggi and A.J. Strojwas, “Model Order-Reduction of RC(L) Interconnect including Variational Analysis”, Proceedings of the Design Automation Conference (Best Paper Award Nomination), June 1999.
M. Beattie and L. Pileggi, “IC Analyses Including Extracted Inductance Models”, Proceedings of the Design Automation Conference, Invited Paper, June 1999.
L. Pileggi, “Achieving Timing Closure for Giga-Scale IC Designs”, 1999 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Invited Paper, March 1999.
E. Acar, A. Odabasioglu, M. Celik and L. Pileggi, “S2P: Stable 2-Pole Model for RC Interconnect Delay Analysis”, Proceedings of the 9th Great Lakes Symposium on VLSI, March 1999.
M. Beattie, L. Alatan and L. Pileggi, “Equipotential Shells for Efficient Partial Inductance Extraction”, Proceedings of the International Electronics Devices Meeting, December 1998.
P. Gross, R. Arunachalam, K. Rajagopal and L. Pileggi, “Determination of Worst-Case Aggressor Alignment for Delay Calculation”, Proceedings of the International Conference on Computer-Aided Design, November 1998.
T. Lin, Emrah Acar and L. Pileggi, “h-gamma: An Interconnect Timing Metric Based on the Gamma Distribution Model for the Homogeneous Response”, Proceedings of the International Conference on Computer-Aided Design, November 1998.
F. Liu, L. Pileggi and A.J. Strojwas, “A Synthesized Driving-Point Model for Capacitively Coupled Interconnects”, Proceedings of the SRC Techcon Conference, September 1998.
K. Rajagopal, P. Gross and L. Pileggi, “The Impact of Coupling on Worst-Case Waveform Analysis”, Proceedings of the SRC Techcon Conference, September 1998.
T. Lin and L. Pileggi, “Looking Beyond the Elmore Delay — Metrics for Deep Submicron”, Proceedings of the SRC Techcon Conference, September 1998.
M. Beattie and L. Pileggi, “Equipotential Shells for Efficient Inductance Extraction”, Proceedings of the SRC Techcon Conference, September 1998.
Florin Dartu and Lawrence Pileggi, “TETA: Transistor-Level Engine for Timing Analysis”, Proceedings of the Design Automation Conference, June 1998.
Frank Liu, Lawrence Pileggi and Andrzej Strojwas, ftd: “An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models”, Proceedings of the Design Automation Conference, June 1998.
Rony Kay and Lawrence Pileggi, “PRIMO: Probability Interpretation of Moments for Delay Calculation”, Proceedings of the Design Automation Conference, June 1998.
L. Pileggi, “Timing Metrics for Physical Design of Deep Submicron Technologies”, Invited paper, International Symposium on Physical Design, April 1998.
Zhijiang (John) He and Lawrence T. Pileggi, “A Simple Algorithm for Calculating Frequency-Dependent Inductance Bounds”, Proceedings of the Custom Integrated Circuits Conference, May 1998.
G. Ellis, L.T. Pileggi, R.A. Rutenbar, “A Hierarchical Decomposition Methodology for Multistage Clock Circuits”, Proceedings of the International Conference on Computer-Aided Design, 1997.
A. Odabasioglu, M. Celik, L.T. Pileggi, “PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm”, Proceedings of the International Conference on Computer-Aided Design, 1997.
A. Mehta, Y-P. Chen, N. Menezes, L. T.Pileggi and M. Wong, “Clustering and Load Balancing for Buffered Clock Tree Synthesis”, Proceedings of the Int’l Conference on Computer Design, October 1997.
Ravishankar Arunachalam, Florentin Dartu and Lawrence T.Pileggi, “CMOS Gate Delay Models for General RLC Loading”, Proceedings of the Int’l Conference on Computer Design, October 1997.
John He, Mustafa Celik and Lawrence Pileggi, “SPIE: Sparse PEEC Inductance Extraction”, Proceedings of the Design Automation Conference, 1997.
Michael Beattie and Lawrence Pileggi, “Bounds for BEM Capacitance Extraction”, Proceedings of the Design Automation Conference, 1997.
Florin Dartu and Lawrence Pileggi, “Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling”, Proceedings of the Design Automation Conference, 1997.
R. Kay, G. Bucheuv, and L. Pileggi, “EWA: Exact Wire Sizing Algorithm”, 1997 International Symposium on Physical Design, April 1997.
G. Ellis, L. Pileggi and R. Rutenbar, “A Hierarchical Decomposition Methodology for Single-Stage Clock Circuits”, Proceedings of the Custom Integrated Circuits Conference, May 1997.
F. Liu, L. Pileggi and A.J. Strojwas, “A Sparse Macromodeling Method for RC Interconnect Multiports”, Proceedings of the Custom Integrated Circuits Conference, May 1997.
F. Dartu and L.T. Pileggi, “Gate-level modeling of of coupling capacitance effects”, Proceedings of the SRC Techcon Conference, October 1996.
Florentin Dartu and Lawrence T. Pileggi, “Modeling Signal Waveshapes for Empirical CMOS Gate Delay Models”, Sixth International Workshop on Power and Timing Modeling, Optimization and Simulation, September 1996.
Florin Dartu, Bogdan Tutuianu and Lawrence T. Pileggi, “RC-Interconnect Macromodels for Timing Simulation”, Proceedings of the Design Automation Conference , 1996.
Bogdan Tutuianu and Lawrence Pileggi, “An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response”, Proceedings of the Design Automation Conference , 1996.
Byron Krauter, Yu Xia, Aykut Dengi, Lawrence T. Pileggi, “A Sparse Image Method for BEM Capacitance Extraction”, Proceedings of the Design Automation Conference, 1996.
Xun Yang, Byron Krauter and L. Pileggi, “Combined ac and Transient Power Distribution Analysis”, Proceedings of the Custom Integrated Circuits Conference, May 1996.
R. Gupta, B. Krauter and L. Pileggi, “On Moment Based Metrics for Optimal Termination of Transmission Line Interconnects”, Proceedings of the 9th International Conference on VLSI Design, January 1996.
M. Kamon, B. Krauter, J. Phillips, L. Pileggi, and J. White, “Two Optimizations to Accelerated Method-of-Moments Algorithms for Signal Integrity Analysis of Complicated 3-D Packages”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, November 1995.
R. Gupta and L. Pileggi, “Constrained Multivariable Optimization of Transmission Lines with General Topologies”, Proceedings of the International Conference on Computer-Aided Design, 1995.
N. Menezes, R. Baldick and L. Pileggi, “A Sequential Quadratic Programming Approach to Concurrent Gate and Wire Sizing”, Proceedings of the International Conference on Computer-Aided Design, 1995.
B. Krauter and L. Pileggi, “Generating Sparse Partial Inductance Matrices with Guaranteed Stability”, Proceedings of the International Conference on Computer-Aided Design, 1995.
L. Pileggi, “Coping with RC(L) Interconnect Induced Headaches”, Proceedings of the International Conference on Computer-Aided Design, (Invited Tutorial Paper) 1995.
I. Tesu and L. Pileggi, “Pre-characterization of ECL Gates for Timing Analysis”, SCS ’95 International Symposium on Signals, Circuits & Systems, Iasi, Romania, October 1995.
I. Tesu and L. Pileggi, “Timing Analysis Models for Gates and Cells with Bipolar Transistor Output Stages”, Proceedings of the IEEE ASIC Conference, 1995.
B. Krauter, R. Gupta, J. Willis and L. Pileggi, “Transmission Line Synthesis”, Proceedings of the Design Automation Conference , 1995.
N. Menezes, S. Pullela and L. Pileggi, “Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization”, Proceedings of the Design Automation Conference, 1995.
R. Gupta, B. Krauter, B. Tutuianu, J. Willis and L. Pileggi, “The Elmore Delay as a Bound for RC-Trees with Generalized Input Signals”, Proceedings of the Design Automation Conference, 1995.
S. Pullela, N. Menezes and L.T. Pillage, “Low Power IC Clock Tree Design”, Proceedings Custom Integrated Circuits Conference, May 1995.
B. Krauter, D. Neikirk and L.T. Pillage, “Sparse Partial Inductance Matrix Formulation”, Progress in Electromagnetics Research Symposium, July 1995.
Rohini Gupta, John Willis and L.T. Pillage, “Wire Width Optimization of Transmission Lines for Low Power Design”, IEEE Multi-chip Module Conference, February 1995.
L.T. Pillage and R.A. Rohrer, “The Essence of AWE”, Circuits and Devices Magazine, November 1994.
John Willis, Rohini Gupta and L.T. Pillage, “Metrics for RLC Transmission Line Termination”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, November 1994.
N. Menezes, S. Pullela and L.T. Pillage, “RC Interconnect Synthesis — A Moment Fitting Approach”, Proceedings of the 1994 International Conference on Computer-Aided Design, Nov. 1994.
R. Gupta, S.Y. Kim and L.T. Pillage, “Domain Characterization of Transmission Line Models for Efficient Simulation”, Proceedings of the International Conference on Computer Design, October 1994.
R. Gupta and L.T. Pillage, “OTTER: Optimal Termination of Transmission Lines Excluding Radiation”, Proceedings Design Automation Conference, June 1994.
F. Dartu, N. Menezes, J. Qian and L.T. Pillage, “A Gate Delay Model for High Performance CMOS”, Proceedings Design Automation Conference, June 1994.
R.B. Brashear, N. Menezes, C. Oh, L.T. Pillage and M.R. Mercer, “Predicting Circuit Performance Using Circuit-Level Statistical Timing Analysis”, Proceedings of the European Design Automation Conference, February 1994.
S. Y. Kim, E. Tuncer, R. Gupta, B. Krauter, T.L. Savarino, D. P. Neikirk and L. T. Pillage, “An Efficient Methodology for Extraction and Simulation of Transmission Lines for Application Specific Electronic Modules”, Proceedings of the 1993 International Conference on Computer-Aided Design, Nov. 1993.
S. Pullela, N. Menezes and L.T. Pillage, “Skew and Delay Optimization for Reliable Buffered Clock Trees”, Proceedings of the 1993 International Conference on Computer-Aided Design, Nov. 1993.
E. Tuncer, S.Y. Kim, L.T. Pillage and D. Neikirk, A New, “Efficient Circuit Model for Microstrip Lines Including Both Current Crowding and Skin Depth Effects”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, October 1993.
D.C. Yuan, L.T. Pillage, and J.T. Rahmeh, “Evaluation by Parts of Mixed-Level dc- Connected Components in Logic Simulation”, Proceedings Design Automation Conference, June 1993.
S. Pullela, N. Menezes and L.T. Pillage, “Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization”, Proceedings Design Automation Conference, June 1993.
N. Menezes, S. Pullela, A. Balivada and L.T. Pillage, “Skew Reduction in Clock Trees Using Wire Width Optimization”, Proceedings Custom Integrated Circuits Conference, May 1993.
V. Raghavan, R.A. Rohrer, L.T. Pillage, J.Y. Lee, J.E. Braken, M.M. Alaybeyi, AWE-Inspired, “Proceedings Custom Integrated Circuits Conference”, (Invited Tutorial Paper), May 1993.
S.Y. Kim, N. Gopal and L.T. Pillage, “Finite-Pole Macromodels of Transmission Lines for Circuit Simulation”, Proceedings Custom Integrated Circuits Conference, May 1993.
R. Brashear, D. Holberg, M.R. Mercer and L.T. Pillage, “ETA: Electrical-Level Timing Analysis”, Proceedings IEEE International Conference on Computer-Aided Design, November 1992.
S.Y. Kim, N. Gopal and L.T. Pillage, “AWE Macromodels for Incorporation in a Circuit Simulator”, Proceedings IEEE International Conference on Computer-Aided Design, November 1992.
M. Becker, D. Beer, M.J. Gonzalez, C.M. Maziar, L.T. Pillage, M.D. Shermis, T.J. Wagner, G.L. Wise, “Introduction to Electrical and Computer Engineering”, Proceedings of the 1992 American Society on Engineering Education Annual Conference, November 1992
D. F. Anastasakis, N. Gopal, S.Y. Kim and L.T. Pillage, “On the Stability of Moment Matching Approximations in Asymptotic Waveform Evaluation”, Proceedings Design Automation Conference, June 1992.
C. Ratzlaff, S. Pullela and L.T. Pillage, “Effects of RC-Interconnect in a Hierarchical Timing Analyzer”, Proceedings Custom Integrated Circuits Conference, May 1992.
N. Gopal, E. Tuncer, D. Neikirk and L.T. Pillage, “Non-Uniform Models for Transmission Line Analysis”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, April, 1992.
N. Gopal, D. Neikirk and L.T. Pillage, “Evaluating RC Interconnect Using Moment Methods” Proceedings IEEE International Conference on Computer-Aided Design, November 1991.
N. Gopal, C. Ratzlaff, L.T. Pillage, “Constrained Approximation of Dominant Time Constants in RC Circuit Delay Models”, Proceedings of the International Mathematics and Computation Symposium, (Invited Paper), July 1991.
C. Ratzlaff, N. Gopal, L.T. Pillage, “RICE: Rapid Interconnect Circuit Evaluator”, Proceedings Design Automation Conference, (Best Paper Award Nomination), June 1991.
A. Balivada, D. Holberg and L.T. Pillage, “Calculation and Application of Time-Domain Sensitivities in Asymptotic Waveform Evaluation”, Proceedings Custom Integrated Circuits Conference, May 1991.
D. Holberg, S. Dutta and L.T. Pillage, “DC Parametrized Piecewise Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation”, Proceedings IEEE International Conference on Computer-Aided Design, November 1990.
S. Dutta and L.T. Pillage, “Calculating the Moments in AWE With Linear Complexity”, Proceedings of the SRC Techcon Conference, October 1990.
L.T. Pillage and S. Dutta, “A Path Tracing Algorithm for Asymptotic Waveform Evaluation of RLC Circuit Delay Models”, 1990 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, August 1990.
L.T. Pillage, X. Huang and R.A. Rohrer, “Asymptotic Waveform Evaluation for Circuits Containing Floating Nodes”, Proceedings IEEE International Symposium on Circuits and Systems, May 1990.
L.T. Pillage, X. Zhang and R.A. Rohrer, “Efficient Final Placement Based on Nets-as- Points”, Proceedings Design Automation Conference, June 1989.
L.T. Pillage, X. Huang and R.A. Rohrer, “AWEsim: Asymptotic Waveform Evaluation for Timing Analysis”, Proceedings Design Automation Conference, June 1989.
L.T. Pillage, C. Wolff and R.A. Rohrer, “Frequency Response Simulation”, Proceedings Custom Integrated Circuits Conference, May 1989.
L.T. Pillage and R.A. Rohrer, “Delay Evaluation with Lumped Linear RLC Interconnect Circuit Models”, Proceedings Decennial Caltech Conference on VLSI, March 1989.
L.T. Pillage and R.A. Rohrer, “A Quadratic Metric for the Initial Placement Problem with a Simple Solution Scheme”, Proceedings Design Automation Conference, June 1988.
L.T. Pillage, X. Huang and R.A. Rohrer, “TALISMAN: A Piecewise Linear Circuit Simulator Based on Tree Link Analysis”, Proceedings IEEE International Conference on Computer-Aided Design, November 1987.
L.T. Pillage, X. Huang and R.A. Rohrer, “Tree Link Partitioning for the Implicit Solution of Circuits”, Proceedings IEEE International Symposium on Circuits and Systems, May 1987.
Agarwal, A. Pandey, and L. Pileggi, “Continuous Switch Model and Heuristics for Mixed-Integer Nonlinear Problems in Power Systems,” IEEE Transaction on Power Systems, doi: 10.1109/TPWRS.2023.3340113.
S. (Cindy) Li, A. Pandey, and L. Pileggi, ” A Convex Method of Generalized State Estimation using Circuit-theoretic Node-breaker Model,” in IEEE Transactions on Power Systems, November 2023, pp. 1-14, doi: 10.1109/TPWRS.2023.3333757.
Agarwal, N. Turner-Bandele, A. Pandey, and L. Pileggi, “Generalized Smooth Functions for Modeling Steady-State Response of Controls in Transmission and Distribution,” Electric Power Systems Research, 2022, CorpusID:252317429.
S. (Cindy) Li, A. Pandey, B. Hooi, C. Faloutsos and L. Pileggi, “Dynamic Graph-Based Anomaly Detection in the Electrical Grid,” in IEEE Transactions on Power Systems, vol. 37, no. 5, pp. 3408-3422, Sept. 2022, doi: 10.1109/TPWRS.2021.3132852.
Agarwal, L. Pileggi, “Large Scale Multi-Period Optimal Power Flow with Energy Storage Systems Using Differential Dynamic Programming,” IEEE PES Transactions on Power Systems, 2021.
S. Pagliarini, J. Sweeney, K. Mai, S. Blanton, S. Mitra and L. Pileggi, “Split-Chip Design to prevent IP Reverse Engineering,” in IEEE Design & Test, doi: 10.1109/MDAT.2020.3033255.
Jovicic, M. Jereminov, L. Pileggi, Gabriela Hug, Enhanced Modelling Framework for Equivalent Circuit-Based Power System State Estimation, IEEE Transactions on Power Systems, February 2020 (10.1109/TPWRS.2020.2974459).
Jereminov, D.M. Bromberg, A. Pandey, M.R. Wagner, and L. Pileggi, “Evaluating Feasibility within Power Flow,” IEEE Transactions on Smart Grid, Vol. 11, No. 4, July 2020. DOI: 10.1109/TSG.2020.2966930.
M. Isgenc, M. Martins, S. Pagliarini and L. Pileggi, “Logic IP for Low-Cost IC Design in Advanced CMOS Nodes,” IEEE Transactions on Very Large Scale Integration, Vol 28, Issue 2, February 2020. (DOI:10.1109/TVLSI.2019.2942825.)
A. Pandey and L. Pileggi, “Steady-State Simulation for Combined Transmission and Distribution Systems,” in IEEE Transactions on Smart Grid, Vol 11, Issue 2, March 2020. (DOI: 10.1109/TSG.2019.2932403).
S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 39, Issue 2, February 2020. DOI (10.1109/TCAD.2018.2889772)
I. Karageorgos, M. Isgenc, S. Pagliarini, and L. Pileggi, Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography, Journal of Hardware and Systems Security, November 2019 (DOI: 10.1007/s41635-019-00080-y).
S. Pagliarini, S. Bhuin, M. Isgenc, A. Biswas, L. Pileggi, A Probabilistic Synapse with Strained MTJs for Spiking Neural Networks, IEEE Transactions on Neural Networks and Learning Systems, June 2019.
A. Pandey, M. Jereminov, M. R. Wagner, D. M. Bromberg, G. Hug, L. Pileggi, Robust Power Flow and Three Phase Power Flow Analyses, IEEE Transactions on Power Systems, Vol. 34, Issue:1, pp. 616-626, January 2019.
M. Jereminov, A. Pandey, L. Pileggi, Equivalent Circuit Formulation for Solving AC Optimal Power Flow, IEEE Transactions on Power Systems, December 2018.
S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, December 2018.
S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “Application and Product-Volume Specific Customization of BEOL Metal Pitch,” IEEE Transactions on VLSI, Vol. 26, Issue:9, pp. 1627-1636, September 2018.
S. Liu, T. Rabuske, J. Paramesh, L. Pileggi, and J. Fernandes, “Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs”, IEEE Transactions on Circuits and Systems I, Vol. 65, No. 2, pp. 458-470, February 2018.
M. Darwish, V. Calayir, L. Pileggi, J. Weldon, “Ultra-Compact Graphene Multigate Variable Resistor for Neuromorphic Computing”, IEEE Transactions on Nanotechnology, Vol. 15, No. 2, March 2016.
R. Liu and L. Pileggi, “Low-Overhead Self-Healing Methodology for Current Matching in Current-Steering DAC”, IEEE Transactions on Circuits and Systems II, vol 62, no. 7, pp. 651-655, July 2015.
K. Vaidyanathan, Q. Zhu, L. Liebmann, K. Lai, S. Wu, R. Liu, Y. Liu, A.J. Strojwas, and L. Pileggi, “Exploiting Sub-20 nm CMOS Technology Challenges to Design Affordable SoCs”, Journal of Micro/Nanolithography, J. Micro/Nanolith. MEMS MOEMS, 14(1), 011007, July 2015.
R. Liu, L. Pileggi and J. A. Weldon, “A Wideband RF Receiver with Extended Statistical Element Selection Based Harmonic Rejection Calibration”, Integration the VLSI Journal, June 2015.
T. C. Jackson, A. A. Sharma, J. A. Bain, J. A. Weldon, L. Pileggi, “Oscillatory Neural Networks based on TMO Nano-Oscillators and Multi-Level RRAM Cells”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), June 2015.
V. Calayir and L. Pileggi, “Device Requirements and Technology-driven Architecture Optimization for Analog Neurocomputing”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 5, no. 2, pp. 162-173, June 2015.
D. M. Bromberg, H. E. Sumbul, J.-G. Zhu, L. Pileggi, “All-Magnetic MRAM Based on Four Terminal mCell Device”, Journal of Applied Physics, May 2015.
V. H-C. Chen and L. Pileggi, “A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI”, Special Issue of the IEEE Journal on Solid State Circuits (Invited Paper), vol.49, no.12, pp.2891,2901, Dec. 2014.
S. Sun, F. Wang, S. Yaldiz, X. Li, L. Pileggi, A. Natarajan, M. Ferriss, J.-O. Plouchart, B. Sadhu, B. Parker, A. Valdes Garcia, M.A.T. Sanduleanu, J. Tierno, and D. Friedman, “Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits”, IEEE Transactions on Circuits and Systems, vol.61, no.8, pp.2243,2252, Aug. 2014.
K. Vaidyanathan, R. Liu, L. Liebmann, K. Lai, A. Strojwas, L. Pileggi, “Design Implications of Extremely Restricted Patterning”, Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol 13 (03), 2014.
C.Y. Wen, G. Slovin, J. Bain, E. Schlesinger, L. Pileggi and J. Paramesh, “A Phase-Change Via-Reconfigurable CMOS LC VCO”, IEEE Transactions on Electron Devices, Vol. 60, No. 12, pp 3979-3988, December 2013.
D.H. Morris, D.M. Bromberg, J-G. ZHU and L. Pileggi, “Spintronic Devices and Circuits for Low-Voltage Logic”, International Journal of High Speed Electronics and Systems Vol. 21, No. 1 (2012) 1250005.
B. Sadhu, M.A. Ferriss, A.S. Natarajan, S. Yaldiz, J-O. Plouchart, A.V. Rylyakov, A. Valdes-Garcia, B.D. Parker, A. Babakhani, S. Reynolds, X. Li, L. Pileggi, R. Harjani, J. Tierno and D. Friedman, “A Linearized Low Noise VCO-Based PLL With Automatic Biasing”, IEEE Journal of Solid State Circuits (Invited), Volume 48 , Issue 5, May 2013.
D. Bromberg, D. Morris, L. Pileggi and J. Zhu, “All-Magnetic, Nonvolatile, Addressable Chainlink Memory”, IEEE Transactions on Magnetics, vol. 49, no. 7, 2013.
V. Sokalski, D. Bromberg, D. Morris, M. T. Moneck, E. Yang, L. Pileggi, and J-G. Zhu, “Naturally Oxidized FeCo as a Magnetic Coupling Layer for Electrically Isolated Read/Write Paths in mLogic”, IEEE Transactions on Magnetics, vol. 49, no. 7, 2013.
Q. Zhu, C. Berger, E. Turner, L. Pileggi and F. Franchetti, “Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation”, Journal of Signal Processing Systems, 2012.
D. Bromberg, D. Morris, L. Pileggi, J.-G. Zhu, “Novel STT-MTJ device enabling all-metallic logic circuits”, IEEE Transactions on Magnetics, INTERMAG, 2012.
M. Althoff, A. Rajhans, B. Krogh, S. Yaldiz, X. Li, and L. Pileggi, “Formal Verification of Phase-Locked Loops Using Reachability Analysis and Continuization”, Communications of the ACM (invited paper), 2012.
Gokce Keskin, Jon Proesel and Larry Pileggi, “8-bit Flash ADC Design Based on Post-Manufacturing Statistical Element Selection”, IEEE Journal of Solid State Circuits (Invited), Volume 46 , Issue 8, May 2011.
Tejas Jhaveri, Vyacheslav Rovner, Lars Liebmann, Larry Pileggi, Andrzej Strojwas, Jason D. Hibbeler, “Design Technology Co-optimization for Predictive Technology Scaling Beyond Gratings, Invited Keynote Paper”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 4, April 2010.
Xin Li, Jiayong Le, Mustafa Celik and Lawrence Pileggi, “Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 6, pp. 1041-1054, June 2008.
Xin Li, Yaping Zhan and Lawrence Pileggi, “Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 5, pp. 831-843, May 2008.
Benton Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence Pileggi, Rob Rutenbar and Kenneth Shepard, “Digital circuit design challenges and opportunities in the era of nanoscale CMOS”, Proceedings of The IEEE (PTI), vol. 96, no. 2, pp. 343-365, February 2008.
Xin Li, Jiayong Le, Lawrence Pileggi, “Statistical Performance Modeling and Optimization”, Foundations and Trends in Electronic Design Automation: Vol. 1: No 4, pp 331-480, January 2007.
Tejas Jhaveri, Vyacheslav Rovner, Larry Pileggi, Andrzej J. Strojwas, et al., “Maximization of Layout Printability/Manufacturability by Extreme Layout Regularity”, Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol 6 (03), January 2007.
Xin Li, Jiayong Le, Padmini Gopalakrishnan and Lawrence Pileggi, “Asymptotic probability extraction for non-Normal performance distributions”, IEEE Trans. on Computer-Aided Design of Integrated Circuits (TCAD), January 2007.
Xin Li, Padmini Gopalakrishnan, Yang Xu and Lawrence Pilegg, “Robust analog/RF circuit design with projection-based performance modeling”, IEEE Trans. on Computer-Aided Design of Integrated Circuits (TCAD), January 2007.
P. Li, L. Pileggi, M. Ashegi, R. Chandra, “Efficient Full-Chip Thermal Modeling and Analysis”, IEEE Transactions on CAD, Vol. 25, Issue 9, pp. 1763 – 1776, Sept. 2006.
P. Li and L. T. Pileggi, “Compact Reduced-Order Modeling of Weakly Nonlinear Analog and RF Circuits”, IEEE Transactions on Computer-Aided Design, Vol. 23, No. 2, pp. 184-203, February 2005.
Yang Xu, Larry Pileggi, Stephan Boyd, “ORACLE: Optimization with Recourse of Analog Circuits including Layout Extraction”, August 2004
Y. Xu, C. Boone and L. Pileggi, “IEEE Journal of Solid State Circuits”, Volume: 39, Issue: 8, pp. 1347-1351, Aug. 2004.
M. Beattie and L.T. Pileggi, “Parasitic Extraction with Multipole Refinement”, IEEE Transactions on Computer-Aided Design, Vol. 23, (5 pages), February 2004.
P. Li and L. T. Pileggi, “Efficient Per-Nonlinearity Distortion Analysis for Analog and RF Circuits”, IEEE Transactions on Computer-Aided Design, Vol. 22, No. 10, pp. 1297-1309, October 2003.
H. Zheng, B. Krauter and L.T. Pileggi, “Electrical Modeling of Integrated-Package Power/Ground Distributions”, IEEE Design and Test, Volume: 20 Issue: 3, pp. 23-31, May-June 2003.
D. Pandini, L. T. Pileggi and A.J. Strojwas, “Global and Local Congestion Optimization in Technology Mapping”, IEEE Transactions on Computer-Aided Design, Vol. 22, No. 4, pp. 498-506, April 2003.
M. Beattie and L.T. Pileggi, “On-Chip Induction Modeling: Basics and Advanced Methods”, Special Issue of IEEE Transactions on VLSI Systems, vol. 10, No. 6, pp. 712-729, December 2002.
R. Arunachalam, R. D. Blanton, L. T. Pileggi, “Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation”, VLSI Design (Special Issue on TimingAnalysis and Optimization for DSM ICs), Vol.15, pp. 605-618, May 2002.
E. Acar, F. Dartu and L. T. Pileggi, “TETA: Transistor level Waveform Evaluation for Timing Analysis”, IEEE Transactions on Computer-Aided Design, Vol. 21, No. 5, May 2002.
P. Gopalakrishnan, A. Odabasioglu, L. T. Pileggi, and S. Raje, “Overcoming Wireload Model Uncertainty for Physical Design”, IEEE Transactions on Computer-Aided Design, Vol. 21, No. 1, January 2002.
Y. Liu, L. T. Pileggi and A.J. Strojwas, “ftd: Frequency to Time Domain Conversion for Reduced Order Interconnect Circuits”, IEEE Transactions on Circuits and Systems, April 2001.
R.E. Bryant, K.T. Cheng, A.B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. Rabaey and A. Sangiovanni-Vincentelli, “Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI”, Proceedings of the IEEE, Special Issue on the Limits of Semiconductor Technology, pp. 341-366, March 2001.
M. Beattie, B. Krauter, L. Alatan and L. Pileggi, “Equipotential Shells for Efficient Inductance Extraction”, IEEE Transactions on Computer-Aided Design, Vol. 20, No. 1, January 2001.
M. Celik and L. T. Pileggi, “Metrics and Bounds for Phase Delay and Signal Attenuation in RCL Clock Trees”, IEEE Transactions on Computer-Aided Design, Vol. 18, No. 3, pp. 293-300, March 1999.
M. Beattie and L. T. Pileggi, “Bounds for BEM Capacitance Extraction”, IEEE Transactions on Computer-Aided Design, Vol. 18, No. 3, pp. 311-321, March 1999.
Rohini Gupta, John Willis and L.T. Pileggi, “Analytic Termination Metrics for Pin-to- Pin Lossy Transmission Lines with Nonlinear Drivers”, IEEE Transactions on VLSI Systems, Vol. 6, No. 3, pp. 457-463, September 1998.
A. Odabasioglu, M. Celik and L. T. Pileggi, “PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm”, IEEE Transactions on Computer-Aided Design (1999 IEEE Best Paper Award), Vol. 17, No. 8, pp. 645-654, August 1998.
R. Kay and L. Pileggi, EWA: “Efficient Wire Sizing Algorithm”, IEEE Transactions on Computer-Aided Design, January, 1998.
M. Celik and L. T. Pileggi, “Simulation of Lossy Multiconductor Transmission Lines Using Backward Euler”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 45, No. 3, pp. 238-243, March 1998.
N. Menezes, R. Baldick and L.T. Pileggi, “A Sequential Quadratic Programming Approach to Concurrent Gate and Interconnect Sizing”, IEEE Transactions on Computer- Aided Design, August 1997.
S. Pullela, N. Menezes and L.T. Pileggi, “Moment-Sensitivity-Based Wire Sizing for Skew Reduction in On-Chip Clock Nets”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 2, pp. 210-215, February 1997.
Rohini Gupta, Byron Krauter and Lawrence Pileggi, “Transmission Line Synthesis via Constrained Multivariable Optimization”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 6-19, January 1997.
Rohini Gupta, Bogdan Tutuianu and Lawrence Pileggi, “The Elmore Delay as a Bound for RC Trees with Generalized Input Signals”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 95-104, January 1997.
Rohini Gupta and Lawrence Pileggi, “Modeling Lossy Transmission lines Using the Method of Characteristics”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 43, No. 7, pp. 580-583, July 1996.
S. Pullela, N. Menezes and L.T. Pileggi, “Post-Processing of Clock Trees via Wiresizing and Buffering for Robust Design”, IEEE Transactions on Computer-Aided Design, pp. 691-701, June 1996.
Rohini Gupta, John Willis and Lawrence T. Pileggi, “Low Power Design of Off-Chip Drivers and Transmission lines: A Branch and Bound Approach”, International Journal of High Speed Electronics and Systems, Vol. 7, no. 9, pp. 27-45, June 1996.
F. Dartu, N. Menezes and L.T. Pileggi, “Performance Computation for Pre-characterized CMOS Gates with RC Loads”, IEEE Transactions on Computer-Aided Design, pp. 544-553, May 1996.
Rohini Gupta, Seok-Yoon Kim and Lawrence Pileggi, “Domain Characterization of Transmission Line Models and Analyses”, IEEE Transactions on Computer-Aided Design, pp. 184-193, February 1996.
J. Qian, S. Pullela and L.T. Pillage, Modeling the “Effective Capacitance” of RC Interconnect, IEEE Transactions on Computer-Aided Design, pp. 1526-1535, December 1994.
S.Y. Kim, N. Gopal and L.T. Pillage, “Time-Domain Macromodels for VLSI Interconnect Analysis”, IEEE Transactions on Computer-Aided Design, pp. 1257-1270, October 1994.
C. Ratzlaff and L.T. Pillage, “RICE: Rapid Interconnect Circuit Evaluation Using Asymptotic Waveform Evaluation”, IEEE Transactions on Computer-Aided Design, pp. 763-776, June 1994.
D.F. Anastaskis, N. Gopal, S.Y. Kim and L.T. Pillage, “On the Stability of Moment- Matching Approximations in Asymptotic Waveform Evaluation”, IEEE Transactions on Computer-Aided Design, pp. 729-736, June 1994.
N. Gopal, A. Balivada and L.T. Pillage, “Moment-Matching Approximations for Linear(ized) Circuit Analysis, Semiconductors in IMA Volumes in Mathematics and it’s Applications”, F. Odeh, J. Cole, W. M. Coughran, Jr., P. Lloyd, and J. White, editors, Springer-Verlag, pp. 115-130, May 1994.
Lawrence T. Pillage, “An Early Introduction to Circuit Simulation Techniques, IEEE Transactions on Education”, February 1993.
L.T. Pillage and R.A. Rohrer, “Asymptotic Waveform Evaluation”, IEEE Transactions on Computer-Aided Design (1991 IEEE Best Paper Award), pp. 352-366, April 1990.
- U.S. Patent No. – High Performance Merge Sort with Scalable Parallelization and Full-Throughput Reduction – Sadi, Franchetti, Pileggi, October 27, 2021.
- U.S. Patent No. 10,026,431 – Magnetic shift register – Bromberg, Pileggi, Zhu, July 17, 2018.
- U.S. Patent No. 9,524,767 – Bitcell with Magnetic Switching Elements – Pileggi, Bromberg, Sumbul, December 20, 2016.
- U.S. Patent No. 9,300,301 – A Non-Volatile Magnetic Logic Device –Bromberg, Zhu, Pileggi, Sokalski, Moneck, March 29, 2016.
- U.S. Patent No. 9,286,216 – 3DIC Memory Chips Including Computational Logic-in-Memory for Performing Accelerated Data Processing – Franchetti, Zhu and Pileggi, March 15, 2016.
- U.S. Patent No. 9,117,523 – Chainlink Memory – Morris, Bromberg, Pileggi, Zhu, August 25, 2015.
- U.S. Patent No. 8,589,833 – Method for the Definition of a Library of Application-Domain-Specific Logic Cells – Motiani, Kheterpal and Pileggi, November 19, 2013.
- U.S. Patent No. 8,476,925 – Magnetic Switching Cells and Methods of Making and Operating Same, Patent Application No. 12849595, Zhu and Pileggi, July 2, 2013.
- U.S. Patent No. 8,400,066 – Magnetic Logic Circuits and Systems Incorporating Same, Patent Application No. 12849595, Pileggi and Zhu, March 19, 2013.
- U.S. Patent No. 8,271,916 – Method for the Definition of a Library of Application-Domain-Specific Logic Cells – Motiani, Kheterpal and Pileggi, September 18, 2012.
- U.S. Patent No. 8,198,655 – Regular Pattern Arrays for Memory and Logic on a Semiconductor Substrate – Pileggi and Morris, June 12, 2012.
- U.S. Patent No. 8,082,137 – Method and apparatus for thermal modeling and analysis of semiconductor chip designs – Li, Pileggi, Asheghi and Chandra, December 20, 2011.
- U.S. Patent No. 7,945,868 – Tunable Integrated Circuit Design for Nano-Scale Technologies – Pileggi and Li, May 17, 2011.
- U.S. Patent No. 7,908,131 – Analog and radio frequency (RF) system-level simulation using frequency relaxation – Li, Li and Pileggi, March 15, 2011.
- U.S. Patent No. 7,906,254 – “Method and Process for Design of Integrated Circuits Using Regular Geometry Patterns to Obtain Geometrically Consistent Component Features” – Pileggi, Strojwas and Lanza, March 15, 2011.
- U.S. Patent No. 7,827,516 – Method and System for Grouping Logic in an Integrated Circuit Design to Minimize Number of Transistors and Number of Unique Geometry Patterns – Moe, Pileggi, et al, November 2, 2010.
- U.S. Patent No. 7,757,187 – Method for Mapping a Boolean Logic Network to a Limited Set of Application-Domain Specific Logic Cells – Kheterpal, Pileggi and Motiani, July 13, 2010.
- U.S. Patent No. 7,784,013 – Method for the Definition of a Library of Application-Domain-Specific Logic Cells – Motiani, Kheterpal and Pileggi, August 24, 2010.
- U.S. Patent No. 7,669,150 – Statistical Optimization and Design Method for Analog and Digital Circuits – Li and Pileggi, February 23, 2010.
- U.S. Patent No. 7,653,524 – Analog and radio frequency (RF) system-level simulation using frequency relaxation – Li, Xu, Li and Pileggi, January 26, 2010.
- U.S. Patent No. 7,634,248 – Configurable Circuits Using Phase Change Switches – Xu, Pileggi and Asheghi, December 15, 2009.
- U.S. Patent No. 7,487,486 – Defining Statistical Sensitivity for Timing Optimization of Logic Circuits with Large-Scale Process and Environmental Variations – Celik, Le, Pileggi and Li, February 3, 2009.
- U.S. Patent No. 7,401,304 – Method and Apparatus for Thermal Modeling and Analysis of Semiconductor Chip Designs – Li, Pileggi, Asheghi and Chandra, July 15, 2008.
- U.S. Patent No. 7,350,164 – Optimization and Design Method For Configurable Analog circuits And Devices – Xu, Pileggi and Boyd, March 2008.
- U.S. Patent No. 7,325,180 – System and Method to Test Integrated Circuits on a Wafer – Pileggi, Yue, Blanton and Vogels, January 2008.
- U.S. Patent No. 7,278,118 – “Method and Process for Design of Integrated Circuits Using Regular Geometry Patterns to Obtain Geometrically Consistent Component Features” – Pileggi, Strojwas and Lanza, October 2, 2007.
- U.S. Patent No. 7,096,174 – “Systems, Method and Computer Program Products for Creating Hierarchical Equivalent Circuit Models” – Beattie and Pileggi, August 22, 2006.
- U.S. Patent No. 6,961,916 – “Placement method for integrated circuit design using topo-clustering” – Sarrafzadeh, Pileggi, et al, November 1, 2005.
- U.S. Patent No. 6,820,245 – ” Methods, systems, and computer program products for modeling inductive effects in a circuit by combining a plurality of localized models,” – Beattie and Pileggi, November 16, 2004.
- U.S. Patent No. 6,775,808- “Method and Apparatus for Generating Sign-Off Prototypes for the Design and Fabrication of Integrated Circuits” – Raje, Pileggi, et al, August 10, 2004.
- U.S. Patent No. 6,651,232 – “Method and System for Progressive Clock Tree or Mesh Construction Concurrently with Physical Design” – Pileggi et al, November, 2003.
- U.S. Patent No. 6,633,182 – “Programmable Gate Array Based on Configurable Metal Interconnect Vias” – Pileggi and Schmit, June 2003.
- U.S. Patent No. 6,449,756 – “A Method for Accurate and Efficient Updates of Timing Information During Logic Synthesis, Placement and Routing for Integrated Circuits” – Malik, Pileggi, et al, Sept 2002.
- U.S. Patent No. 6,442,743 – “Placement Method for Integrated Circuit Design using TopoClustering” – Sarrafzadeh, Pileggi, et al, Aug 2002.
- U.S. Patent No. 6,385,760 – “System and Method for Concurrent Placement of Gates and Associated Wiring” – Pileggi, Sarrafzadeh, et al, May 2002.
- U.S. Patent No. 6,367,051 – “System and Method for Concurrent Buffer Insertion and Placement of Logic Gates” – Pileggi, Sarrafzadeh, et al, April 2002.
- U.S. Patent No. 6,286,128 – “Method for Design Optimization using Logic and Physical Information” – Pileggi et al, September 2001.
- U.S. Patent No. 6,192,508 – “Method for Logic Optimization for Improving Timing and Congestion During Placement in Integrated Circuit Design” – Malik, Pileggi et al, Feb. 2001.
- U.S. Patent No. 5,379,231 – “Method and Apparatus for Simulating a Microelectronic Interconnect Circuit” – Pillage, Ratzlaff and Gopal, January 1995.
- U.S. Patent No. 5,023,822 – “Pulse Ratio System” – Schlotterer, Johnston, Rusnak, Pillage, and Byrd.
- U.S. Patent No. 4,683,989 – “Elevator Communications Controller” – Pillage and Anderson, Westinghouse R&D.
C. Talbot, Deepali Garg, L. Pileggi and K. Mai, “An IP-Agnostic Foundational Cell Array Offering Supply Chain Security,” The 61st Design Automation Conference, June 2024.
C. Talbot, Deepali Garg, L. Pileggi and K. Mai, “IP-Agnostic Standard Cell Fabric Offering Tamper Resistance and Supply Chain Resilience,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 2024.
D. Garg, J. Sweeney and L. Pileggi, Quantifying the Efficacy of Logic Locking Methods, International Conference on VLSI Design, Kolkata India, January 2024.
U.S. Patent No. – High Performance Merge Sort with Scalable Parallelization and Full-Throughput Reduction – Sadi, Franchetti, Pileggi, October 27, 2021.
D. Garg, J. Sweeney and L. Pileggi, Quantifying the Efficacy of Logic Locking Methods, International Conference on VLSI Design, Kolkata India, January 2024.
P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Top-Down Synthesis of Soft eFPGA Fabrics Using Standard ASIC Flows,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 29-April 1, 2021.
P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Top-down physical design of soft embedded FPGA fabrics,” In proceedings of FPGA conference, Feb-March 2021.
X. He, S. Liu, S. Kargarrazi, V. Chen, M. Chamanzar, L. Pileggi, “A Multiplexed Active Digital Implantable Neural Probe,” In proceedings of SfN Global Connectome (virtual conference), January 11-13, 2021.
P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Hardware Redaction via Designer-Directed Fine-Grained Soft eFPGA Insertion,” In proceedings of Design and Test in Europe (DATE), February 1-5, 2021.
M. Isgenc, M. Martins, S. Pagliarini and L. Pileggi, “Logic IP for Low-Cost IC Design in Advanced CMOS Nodes,” IEEE Transactions on Very Large Scale Integration, Vol 28, Issue 2, February 2020. (DOI:10.1109/TVLSI.2019.2942825.)
S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 39, Issue 2, February 2020. DOI (10.1109/TCAD.2018.2889772)
I. Karageorgos, M. Isgenc, S. Pagliarini, and L. Pileggi, Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography, Journal of Hardware and Systems Security, November 2019 (DOI: 10.1007/s41635-019-00080-y).
M. Isgenc, M. Martins, S. Pagliarini and L. Pileggi, “Logic IP for Low-Cost IC Design in Advanced CMOS Nodes,” IEEE Transactions on Very Large Scale Integration, Vol 28, Issue 2, February 2020. (DOI:10.1109/TVLSI.2019.2942825.)
S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 39, Issue 2, February 2020. DOI (10.1109/TCAD.2018.2889772)
F. Sadi , Joe Sweeney, T. M. Low, J. C. Hoe, L. Pileggi, F. Franchetti, “Efficient SpMV operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization,” IEEE/ACM International Symposium on Microarchitecture, October 2019.
S. Pagliarini, S. Bhuin, M. Isgenc, A. Biswas, L. Pileggi, A Probabilistic Synapse with Strained MTJs for Spiking Neural Networks, IEEE Transactions on Neural Networks and Learning Systems, June 2019.
S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, December 2018.
S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, December 2018.
S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “Application and Product-Volume Specific Customization of BEOL Metal Pitch,” IEEE Transactions on VLSI, Vol. 26, Issue:9, pp. 1627-1636, September 2018.
T. Jackson, S. Pagliarini and L. Pileggi, “An Oscillatory Neural Network with Programmable Resistive Synapses,” in 28 nm CMOS, IEEE International Conference on Rebooting Computing, November 2018.
S. Liu, T. Rabuske, L. Pileggi, J. Fernandez, J. Paramesh, “A 125 Ms/S 10.4 ENOB 10.1 fJ/conv-Step Multi-Comparator SAR ADC with Comparator Noise Scaling in 65nm CMOS,” IEEE European Solid-State Circuits conference, September 2018.
S. Liu, T. Rabuske, J. Paramesh, L. Pileggi, and J. Fernandes, “Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs”, IEEE Transactions on Circuits and Systems I, Vol. 65, No. 2, pp. 458-470, February 2018.
E. Calayir, J. Xu, L. Pileggi, G. K. Fedder, N. Singh, S. Merugu and G. Piazza, “Self-healing Narrowband Filters via 3D Heterogeneous Integration of AlN MEMS and CMOS chips”, 2017 IEEE International Ultrasonics Symposium (IUS), Washington, D.C., September 2017.
S. Bhuin, J. Sweeney, S. Pagliarini, A. K. Biswas, L. Pileggi, “A Self-Calibrating Sense Amplifier for A True Random Number Generator Using Hybrid FinFET-Straintronic MTJ”, IEEE International Symposium on Nanoscale Architectures (NANOARCH), July 2017.
T. C. Jackson and L. Pileggi, “A Mixed-Signal Oscillatory Neural Network Architecture for Integration with Resistive Crossbar Memory Arrays”, TECHCON 2017, Austin, Texas.
S. Bhuin and L. Pileggi, “A Self-Calibrating Sense Amplifier for a True Random Number Generator Using Strained MTJ”, TECHCON 2017, Austin, Texas.
S. Bhuin, A. Biswas, L.Pileggi, “Strained MTJs with Latch-based Sensing for Stochastic Computing”, IEEE International Conference on Nanotechnology, July 2017.
J. Xu, G. Piazza, L. Pileggi and G. K. Fedder, “Reconfigurable AlN resonator filter design based on extended statistical element selection” 2017 Transducers – 2017 19th International Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS),Kaohsiung, June 2017.
M. Isgenc, S. Pagliarini, L. Pileggi, “Evaluating the Benefits of a Relaxed BEOL Pitch for Deeply Scaled ICs”, 18th International Symposium on Quality Electronic Design (ISQED), March 2017.
S. Pagliarini, M. Martins, L. Pileggi, “Virtual Characterization for Exhaustive DFM Evaluation of Logic Cell Libraries”, 18th International Symposium on Quality Electronic Design (ISQED), March 2017.
M. Isgenc, M. Martins, S. Pagliarini, L. Pileggi, “Exhaustive DFM evaluation of logic cell libraries via virtual characterization, IEEE/ACM Workshop on Variability Modeling and Characterization”, November 2016.
R. Carley, G. Colak, L. Chomas, L. Pileggi and K. Mai, “Technologies for Secure RFID Authentication of Medicinal Pills and Capsules”, IEEE International Conference on RFID Technology and Applications (RFID-TA), September 2016.
R. Shi, T. Jackson, B. Swenson, S. Kar and L. Pileggi, “On the Design of Phase Locked Loop Oscillatory Neural Networks: Mitigation of Transmission Delay Effects”, International Joint Conference on Neural Networks, July 2016.
R. Liu, J. Weldon and L. Pileggi, “Extended Statistical Element Selection: A Calibration Method for High Resolution in Analog/RF Designs”, Design Automation Conference (DAC 2016), June 2016.
M. Darwish, V. Calayir, L. Pileggi, J. Weldon, “Ultra-Compact Graphene Multigate Variable Resistor for Neuromorphic Computing”, IEEE Transactions on Nanotechnology, Vol. 15, No. 2, March 2016.
Q. Guo, T.-M. Low, N. Alachiotis, B. Akin, L. Pileggi, J.C. Hoe, F. Franchetti, “Enabling Portable Energy Efficiency with Memory Accelerated Library”, 48th Annual IEEE/ACM International Symposium on Microarchitecture, 2015.
F. Wang, S. Yin, M. Jun, X. Li, T. Mukherjee, R. Negi, L. Pileggi, “Re-thinking Polynomial Optimization: Efficient Programming of Reconfigurable Radio Frequency (RF) Systems by Convexification”, Asia and South Pacific Design Automation Conference, January 2016.
K. Vaidyanathan, Q. Zhu, L. Liebmann, K. Lai, S. Wu, R. Liu, Y. Liu, A.J. Strojwas, and L. Pileggi, “Exploiting Sub-20 nm CMOS Technology Challenges to Design Affordable SoCs”, Journal of Micro/Nanolithography, J. Micro/Nanolith. MEMS MOEMS, 14(1), 011007, July 2015.
R. Liu and L. Pileggi, “Low-Overhead Self-Healing Methodology for Current Matching in Current-Steering DAC”, IEEE Transactions on Circuits and Systems II, vol 62, no. 7, pp. 651-655, July 2015.
V. Calayir and L. Pileggi, “Device Requirements and Technology-driven Architecture Optimization for Analog Neurocomputing”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 5, no. 2, pp. 162-173, June 2015.
T. C. Jackson, A. A. Sharma, J. A. Bain, J. A. Weldon, L. Pileggi, “Oscillatory Neural Networks based on TMO Nano-Oscillators and Multi-Level RRAM Cells”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), June 2015.
R. Liu, L. Pileggi and J. A. Weldon, “A Wideband RF Receiver with Extended Statistical Element Selection Based Harmonic Rejection Calibration”, Integration the VLSI Journal, June 2015.
T. C. Jackson, A. A. Sharma, R. Shi, J. Weldon, and L. Pileggi, “Using TMO-based RRAM Multi-Level Cells and Nano-Oscillators for Efficient ONN Implementation”,TECHCON 2015, Austin, Texas.
A. Sharma, T. Jackson, J. Bain, L. Pileggi and J. Weldon, “High Performance, Integrated 1T1R Oxide-based Oscillator: Stack Engineering for Low-Power Operation in Neural Network Applications”,in IEEE Symp. VLSI Technology, June 2015.
H.E. Sumbul, K. Vaidyanathan, Q. Zhu, F. Franchetti, L. Pileggi, “Application-Specific Synthesis of Embedded Logic-in-Memory Designs”, manuscript accepted for publishing in Design Automation Conference (DAC 2015), June 2015.
E. Calayir, J. Xu, A. Patterson, G. K. Fedder, G. Piazza, L. Pileggi, “3D Integration of AlN MEMS Filters and CMOS for Self-Healing RF Front-Ends”,Government Microcircuit Applications and Critical Technology Conference, March 2015.
T. C. Jackson, A. A. Sharma, J. A. Bain, J. A. Weldon, and L. Pileggi, “An RRAM-Based Oscillatory Neural Network”,in Proc. 2015 Latin American Symposium on Circuits and Systems. Montevideo, Uruguay, 2015.
Q. Guo, N. Alachiotis, B. Akin, F. Sadi, G. Xu, T.M. Low, L. Pileggi, J.C. Hoe, and F. Franchetti, “3D-Stacked Memory-Side Acceleration: Accelerator and System Design”, WoNDP: 2nd Int’l Workshop on Near-Data Processing, December 2014.
V. Calayir, M.Darwish, J. Weldon and L. Pileggi, “Analog Neuromorphic Computing Enabled by Multi-Gate Programmable Resistive Devices, Design and Test in Europe” (DATE), March 2015.
D. M. Bromberg, H. E. Sumbul, J.-G. Zhu, L. Pileggi, “All-Magnetic MRAM Based on Four Terminal mCell Device”, Journal of Applied Physics, May 2015.
V. H-C. Chen and L. Pileggi, “A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI”, Special Issue of the IEEE Journal on Solid State Circuits (Invited Paper), vol.49, no.12, pp.2891,2901, Dec. 2014.
S. Sun, F. Wang, S. Yaldiz, X. Li, L. Pileggi, A. Natarajan, M. Ferriss, J.-O. Plouchart, B. Sadhu, B. Parker, A. Valdes Garcia, M.A.T. Sanduleanu, J. Tierno, and D. Friedman, “Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits”, IEEE Transactions on Circuits and Systems, vol.61, no.8, pp.2243,2252, Aug. 2014.
K. Vaidyanathan, R. Liu, L. Liebmann, K. Lai, A. Strojwas, L. Pileggi, “Design Implications of Extremely Restricted Patterning”, Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol 13 (03), 2014.
D. Bromberg, M. Moneck, V. Sokalski, L. Pileggi, J-G. Zhu, “Experimental Demonstration of Four-Terminal Magnetic Logic Device with Separate Read- and Write-Paths, International Electron Devices Meeting”, December 2014.
D.M. Bromberg, E. Sumbul, J-G. Zhu and L. Pileggi, “All-Magnetic MRAM Based on Four Terminal mCell Device”, 13th Joint MMM/Intermag Conference, November 2014.
F. Sadi, B. Akin, D. Popovici, J. Hoe, L. Pileggi, F. Franchetti, “Algorithm/Hardware Co-optimized SAR Image Reconstruction with 3D-stacked Logic in Memory”, Eighteenth Annual High Performance Embedded Computing (HPEC) Workshop at MIT Lincoln Laboratory, September 2014.
R. Liu, L. Pileggi and J. Weldon, “A Wideband RF Receiver with >80 dB Harmonic Rejection Ratio”, Int’l Custom Integrated Circuits Conference, September 2014.
K. Vaidyanathan, L. Liebmann, A. Strojwas, L. Pileggi, “Sub-20 nm Design Technology Co-Optimization for Standard Cell Logic”, Int’l Conference on Computer-Aided Design, November 2014.
T. Jackson, V. Calayir and L. Pileggi, “Integrating Emerging Devices and CMOS for Efficient Cellular Neural Networks”, Proceedings of the SRC Techcon Conference, September 2014.
M. T. Moneck, V. Sokalski, D. M. Bromberg, J. Wu, Z. Dai, L. Pileggi, J.-G. Zhu, “Fabrication Challenges in Developing All-Metal Magnetic Logic Circuits”, 2014 International Magnetics Conference.
J.-G. Zhu, D. Bromberg, V. Sokalski, M.T. Moneck, J. Wu, Z. Dai, L. Pileggi, “mLogic: All Spin Logic Device and Circuits for Future Electronics”, IEEE Transactions on Magnetics, INTERMAG 2014.
V. H-C. Chen and L. Pileggi, “A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI”, International Solid State Circuits Conference (ISSCC), February 2014.
J. Tao, Y.-C. Wang, M. Jun, X. Li, R. Negi, T. Mukherjee, L. Pileggi, “Toward Efficient Programming of Reconfigurable Radio Frequency (RF) Receivers”, 19th Asia and South Pacific Design Automation Conference (ASP-DAC), January 2014.
D.H. Morris, D.M. Bromberg, J-G. ZHU and L. Pileggi, “Spintronic Devices and Circuits for Low-Voltage Logic”, International Journal of High Speed Electronics and Systems Vol. 21, No. 1 (2012) 1250005.
C.Y. Wen, G. Slovin, J. Bain, E. Schlesinger, L. Pileggi and J. Paramesh, “A Phase-Change Via-Reconfigurable CMOS LC VCO”, IEEE Transactions on Electron Devices, Vol. 60, No. 12, pp 3979-3988, December 2013.
Qiuling Zhu, Berkin Akin, H. Ekin Sumbul, James C. Hoe, Larry Pileggi, Franz Franchetti, “A 3D-Stacked Logic-in-Memory Accelerator for Application-Specific Data Intensive Computing”, IEEE International 3D Systems Integration Conference, October 2013.
Qiuling Zhu, Tobias Graf, H. Ekin Sumbul, Larry Pileggi, Franz Franchetti, “A Logic-in-Memory Accelerated 3D-DRAM for Sparse Matrix-Matrix Multiplication”, Seventeenth Annual High Performance Embedded Computing (HPEC) Workshop at MIT Lincoln Laboratory (Best Paper Award), September 2013.
V. Calayir, T. Jackson, A. Tazzoli, G. Piazza and L. Pileggi, “Neurocomputing and Associative Memories Based on Ovenized Aluminum Nitride Resonators”, International Joint Conference on Neural Networks, August 2013.
V. Calayir and L. Pileggi, “All-Magnetic Analog Associative Memory”, International NEWCAS Conference, June 2013.
V. H.-C. Chen and L. Pileggi, “An 8.5mW 5GS/s 6b Flash ADC with Dynamic Offset Calibration in 32nm CMOS SOI”, in IEEE Symp. VLSI Circuits, June 2013.
V. Calayir and L. Pileggi, “Fully-Digital Oscillatory Associative Memories Enabled by Non-volatile Logic”, International Joint Conference on Neural Networks, August 2013.
B. Sadhu, M.A. Ferriss, A.S. Natarajan, S. Yaldiz, J-O. Plouchart, A.V. Rylyakov, A. Valdes-Garcia, B.D. Parker, A. Babakhani, S. Reynolds, X. Li, L. Pileggi, R. Harjani, J. Tierno and D. Friedman, “A Linearized Low Noise VCO-Based PLL With Automatic Biasing”, IEEE Journal of Solid State Circuits (Invited), Volume 48 , Issue 5, May 2013.
D. Bromberg, D. Morris, L. Pileggi and J. Zhu, “All-Magnetic, Nonvolatile, Addressable Chainlink Memory”, IEEE Transactions on Magnetics, vol. 49, no. 7, 2013.
V. Sokalski, D. Bromberg, D. Morris, M. T. Moneck, E. Yang, L. Pileggi, and J-G. Zhu, “Naturally Oxidized FeCo as a Magnetic Coupling Layer for Electrically Isolated Read/Write Paths in mLogic”, IEEE Transactions on Magnetics, vol. 49, no. 7, 2013.
K. Vaidyanathan, L. Liebmann and L. Pileggi, “Rethinking ASIC design with next-generation lithography and process integration”, SPIE Advanced Lithography Conference, February 2013.
D. Bromberg, D. Morris, L. Pileggi and J. Zhu, “All-Magnetic, Nonvolatile, Addressable Chainlink Memory”, 12th Joint MMM/Intermag Conference, January 2013.
V. Sokalski, D.M. Bromberg, D. Morris, M.T. Moneck, E. Yang, L. Pileggi, J-G. Zhu, “Naturally Oxidized FeCo as a Magnetic Coupling Layer for Electrically Isolated Read/Write Paths in mLogic”, 12th Joint MMM/Intermag Conference, January 2013.
Q. Zhu, L. Pileggi and F. Franchetti, Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography, Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October 2012.
J.-O. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakani, S. Yaldiz, L. Pileggi, R. Harjani, S. Reynolds, J. A. Tierno, D. Friedman, “A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS”, Int’l Custom Integrated Circuits Conference, Sept. 2012.
Q. Zhu, L. Pileggi and F. Franchetti, “Smart Memory Synthesis for Energy-Efficient Computed Tomography Reconstruction”, Proceedings of the SRC Techcon Conference, September 2012.
B. Sadhu, M.A. Ferriss, J-O. Plouchart, A.S. Natarajan, A.V. Rylyakov, A. Valdes-Garcia, B.D. Parker, S. Reynolds, A. Babakhani, S. Yaldiz, L. Pileggi, R. Harjani, J. Tierno and D. Friedman, “A 21.8-27.5GHz PLL in 32nm SOI Using Gm Linearization to Achieve -130dBc/Hz Phase Noise at 10MHz Offset from a 22GHz Carrier”, 2012 Radio Frequency Integrated Circuits Symposium, June 2012.
D. Morris, D. Bromberg, J. Zhu and L. Pileggi, “Magnetic Logic Circuits with Minimal Connections to CMOS”, IEEE CAS-FEST, 2012.
D. Morris, D. Bromberg, J. Zhu and L. Pileggi, “mLogic: Ultra-Low Voltage Non-Volatile Logic Circuits Using STT-MTJ Devices”, IEEE/ACM Design Automation Conference (DAC), 2012.
D. Morris, D. Bromberg, J. Zhu, and L. Pileggi, “Spintronic Circuits and Devices for Low-Voltage Electronics”, (Invited Paper) In Proceedings of WOFE, 2011.
Q. Zhu, L. Pileggi , F. Franchetti, “Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography”, VLSI-SoC, October 2012.
D. Bromberg, D. Morris, L. Pileggi and J. Zhu, “Novel STT-MTJ device enabling all-metallic logic circuits”, International Magnetics Conference, May 2012.
K. Vaidyanathan, S.H. NG, D. Morris, N. Lafferty, L. Liebmann, W. Huang, K. Lai, L. Pileggi, A.J. Strojwas, “Design and Manufacturability Tradeoffs in Unidirectional & Bidirectional Standard Cell Images in 14 nm”, SPIE Advanced Lithography Conference, February 2012.
Q. Zhu, C.R. Berger, E. Turner, L. Pileggi, F. Franchetti, “Polar Format Synthetic Aperture RADAR in Energy Efficient Application-Specific Logic-in-Memory”, IEEE International Conference on Acoustics, Speech and Signal Processing, Kyoto Japan, March 2012.
D. Bromberg, D. Morris, L. Pileggi, J.-G. Zhu, “Novel STT-MTJ device enabling all-metallic logic circuits”, IEEE Transactions on Magnetics, INTERMAG, 2012.
D. Morris, D. Bromberg, J. Zhu, and L. Pileggi, “mLogic: Ultra-Low Voltage Logic Circuits with Non-Volatile Spintronic Devices”, (Invited Paper) Workshop on Frontier Electronics, December 2011.
J. Zhu, D. Bromberg, D. Morris and L. Pileggi, “Novel STT Device Design To Enable All Metallic Spin Logic Circuits Free of Transistors”, (Invited Presentation) Conference on Magnetism and Magnetic Materials, October 2011.
Qiuling Zhu, Franz Franchetti and Larry Pileggi, “Application-Specific Logic-in-Memory for Polar Format Synthetic Aperture Radar”, Fifteenth Annual High Performance Embedded Computing (HPEC) Workshop at MIT Lincoln Laboratory, September 2011.
S. Yaldiz, V. Calayir, X. Li, L. Pileggi, et al, “Indirect Phase Noise Sensing for Self-Healing Voltage Controlled Oscillators”, Int’l Custom Integrated Circuits Conference, Sept. 2011.
C.-Y. Wen, J. Paramesh, L. T. Pileggi, J. Li, S. Kim, J. Proesel, C. Lam, “Post-Silicon Calibration of Analog CMOS Using Phase-Change Memory Cells”, European Solid-State Device Research Conference (ESSDERC), September 2011.
C.-Y. Wen, J. Li, S. Kim, M. Breitwisch, C. Lam, J. Paramesh, L. T. Pileggi, “A Non-volatile Look-Up Table Design Using PCM (Phase-Change Memory) Cells”, IEEE Symposium on VLSI, June 2011.
D. Morris, K. Vaidyanathan, N. Lafferty, K. Lai, L. Liebmann, L. Pileggi, “Design of Embedded Memory and Logic Based On Pattern Constructs”, IEEE Symposium on VLSI (Invited Presentation), June 2011.
Gokce Keskin, Jon Proesel and Larry Pileggi, “8-bit Flash ADC Design Based on Post-Manufacturing Statistical Element Selection”, IEEE Journal of Solid State Circuits (Invited), Volume 46 , Issue 8, May 2011.
S. Yaldiz, F. Wang, X. Li, L. Pileggi, A.S. Natarajan, M.A. Ferriss, J. Tierno, “Virtual Phase Noise Sensor for Self-Healing Voltage Controlled Oscillators”, GOMACTech-11 Technical Program, March 2011.
V. Rovner, T. Jhaveri, Daniel Morris, Andrzej J. Strojwas, and Larry Pileggi, “Performance and Manufacturability Trade-offs of Pattern Minimization for sub-22nm Technology Nodes”, SPIE Advanced Lithography Conference, February 2011.
C.-Y. Wen, E. K. Chua, R. Zhao, T. C. Chong, J. A. Bain, T. E. Schlesinger, L. T. Pileggi, J. Paramesh, “A Phase-change via-Reconfigurable On-Chip Inductor”, International Electron Devices Meeting, December 2010.
A. Bonnoit, S. Herbert and L. Pileggi, “Reducing Variability in Chip-Multiprocessors with Adaptive Body Biasing”, International Symposium on Low Power Electronics and Design, August 2010.
J. Proesel, G. Keskin, J.O. Plouchart and L. Pileggi, “An 8-bit 1.5GS/s Flash ADC Using Post-Manufacturing Statistical Selection”, Int’l Custom Integrated Circuits Conference, Sept. 2010.
G. Keskin, J. Proesel and L. Pileggi, “Statistical Modeling and Post Manufacturing Configuration for Scaled Analog CMOS”, Int’l Custom Integrated Circuits Conference, Sept. 2010.
G. Keskin, J. Proesel and L. Pileggi, “Modeling of Statistical Element Selection Based Self-Healing Analog Circuits”, Proceedings of the SRC Techcon Conference, September 2010.
D. Morris, S. Rovner, L. Pileggi, A. Strojwas and K. Vaidyanathan, “Enabling Application-Specific Integrated Circuits on Limited Pattern Constructs”, IEEE Symposium on VLSI (Invited Presentation), June 2010.
L. Liebmann, J. Hibbeler, N. Hieter, L. Pileggi, M. Moe, T. Jhaveri, V. Rovner, “Demonstrating the benefits of template-based design-technology co-optimization”, SPIE Advanced Lithography Conference, February 2010.
T. Jhaveri, A. J. Strojwas, L. Pileggi and V. Rovner, “Economic Assessment of Lithography Strategies for the 22nm Technology Node”, Proceedings of the SPIE/BACUS Symposium on Photomask Technology, September 2009.
U. Arslan, J. Wang and L. Pileggi, “An SRAM Design Framework for Deeply-Scaled CMOS”, Proceedings of the SRC Techcon Conference, September 2009.
J. Proesel, G. Keskin and L. Pileggi, “An 8-bit Flash ADC using Statistical Element Selection”, Proceedings of the SRC Techcon Conference, September 2009.
Tejas Jhaveri, Andrzej Strojwas, Larry Pileggi & Vyacheslav Rovner, “OPC Simplification & Mask Cost Reduction using Regular Design Fabrics”, SPIE Advanced Lithography Conference, February 2009.
Bin Wan, Jian Wang, Gokce Keskin, and Lawrence T. Pileggi, “Ring Oscillators for Single Process-Parameter Monitoring”, IEEE Workshop on Test Structure Design for Variability Characterization, November 2008.
J. Proesel and L. Pileggi, ‘A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS’, Int’l Custom Integrated Circuits Conference, Sept. 2008.
U. Arslan, M. McCartney, M. Bhargava, X. Li, K. Mai and L. Pileggi, “Variation-Tolerant SRAM Sense-Amplifier Timing Using Configurable Replica Bitlines”, Int’l Custom Integrated Circuits Conference, Sept. 2008.
U. Arslan, M. McCartney, M. Bhargava, L. Pileggi and K. Mai, “Variation-Tolerant SRAM Sense-Amp Timing using Configurable Replica Bitlines”, Proceedings of the SRC Techcon Conference, September 2008.
J. Proesel and L. Pileggi, “A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS”, Proceedings of the SRC Techcon Conference, September 2008.
G. Keskin, L. Pileggi, X. Li and K. Mai, “Process Variation Effects on Input Offset Voltage of CMOS SRAM Sense Amplifiers”, Proceedings of the SRC Techcon Conference, September 2008.
Benton Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence Pileggi, Rob Rutenbar and Kenneth Shepard, “Digital circuit design challenges and opportunities in the era of nanoscale CMOS”, Proceedings of The IEEE (PTI), vol. 96, no. 2, pp. 343-365, February 2008.
P. Gopalakrishnan and L. Pileggi, “Timing Driven Initial Placement for FPGAs via Graph Matching”, Proceedings of the SRC Techcon Conference, October 2005.
Y. Xu and L. Pileggi, “Metal-mask Configurable RF Integrated Circuits”, GOMACTech-05 Technical Program, April 2005.
H. Zheng, B. Krauter and L.T. Pileggi, “Electrical Modeling of Integrated-Package Power/Ground Distributions”, IEEE Design and Test, Volume: 20 Issue: 3, pp. 23-31, May-June 2003.
H. Zheng, B. Krauter, L. Pileggi, “On-Package Decoupling Optimization with Package Macromodels”, Int’l Custom Integrated Circuits Conference, Sept. 2003.
K.Y. Tong, V. Kheterapal, S. Rovner, H. Schmit, L. Pileggi, R. Puri, “Regular Logic Fabrics for a Via Patterned Gate Array (VPGA)”, Int’l Custom Integrated Circuits Conference, Sept. 2003.
A. Koorapaty, L. Pileggi, H. Schmit, “Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics”, International Conference on Field Programmable Logic and Applications, September 2003.
C. Patel, A. Cozzie, H. Schmit and L. Pileggi, “An Architecture Exploration of Via Patterned Gate Arrays”, Internation Symposium on Physical Design, April 2003.
A. Koorapaty, V. Chandra, K.Y. Tong, C. Patel, L. Pileggi and H. Schmit, “Heterogeneous Programmable Logic Block Architectures”, Design and Test in Europe Conference (DATE), March 2003.
Shimiao Li, Amritanshu Pandey, and Larry Pileggi. “Contingency Analysis with Warm Starter using Probabilistic Graphical Model.” Power Systems Computation Conference (PSCC), June 2024.
S. Li, J. Drgona, S. Abhyankar, L. Pileggi, Power Grid Behavioral Patterns and Risks of Generalization in Applied Machine Learning, 5th International Workshop on Applied Machine Learning for Intelligent Energy Systems (AMLIES 2023), Orlando FL, June 2023.
E. Foster, T. McNamara, A. Pandey and L. Pileggi, Actionable Three-Phase Infeasibility Optimization with Varying Slack Sources, IEEE PES General Meeting, July 16-20, 2023
Agarwal, A. Pandey, and L. Pileggi, “Continuous Switch Model and Heuristics for Mixed-Integer Nonlinear Problems in Power Systems,” IEEE Transaction on Power Systems, doi: 10.1109/TPWRS.2023.3340113.
S. (Cindy) Li, A. Pandey, and L. Pileggi, ” A Convex Method of Generalized State Estimation using Circuit-theoretic Node-breaker Model,” in IEEE Transactions on Power Systems, November 2023, pp. 1-14, doi: 10.1109/TPWRS.2023.3333757.
Agarwal, N. Turner-Bandele, A. Pandey, and L. Pileggi, “Generalized Smooth Functions for Modeling Steady-State Response of Controls in Transmission and Distribution,” Electric Power Systems Research, 2022, CorpusID:252317429.
S. (Cindy) Li, A. Pandey, B. Hooi, C. Faloutsos and L. Pileggi, “Dynamic Graph-Based Anomaly Detection in the Electrical Grid,” in IEEE Transactions on Power Systems, vol. 37, no. 5, pp. 3408-3422, Sept. 2022, doi: 10.1109/TPWRS.2021.3132852.
Agarwal, L. Pileggi, “Large Scale Multi-Period Optimal Power Flow with Energy Storage Systems Using Differential Dynamic Programming,” IEEE PES Transactions on Power Systems, 2021.
S. (Cindy) Li, A. Pandey, and L. Pileggi, ” A Convex Method of Generalized State Estimation using Circuit-theoretic Node-breaker Model,” in IEEE Transactions on Power Systems, Accepted for Publication.
A. Agarwal, N. Turner-Bandele, A. Pandey, and L. Pileggi, “Generalized Smooth Functions for Modeling Steady-State Response of Controls in Transmission and Distribution,” Electric Power Systems Research, Accepted for Publication.
S. (Cindy) Li, A. Pandey, B. Hooi, C. Faloutsos and L. Pileggi, “Dynamic Graph-Based Anomaly Detection in the Electrical Grid,” in IEEE Transactions on Power Systems, vol. 37, no. 5, pp. 3408-3422, Sept. 2022, doi: 10.1109/TPWRS.2021.3132852
A. Agarwal, L. Pileggi, “Large Scale Multi-Period Optimal Power Flow with Energy Storage Systems Using Differential Dynamic Programming,” IEEE PES Transactions on Power Systems, 2021.
S. Li, J. Drgona, S. Abhyankar, L. Pileggi, Power Grid Behavioral Patterns and Risks of Generalization in Applied Machine Learning, 5th International Workshop on Applied Machine Learning for Intelligent Energy Systems (AMLIES 2023), Orlando FL, June 2023.
E. Foster, T. McNamara, A. Pandey and L. Pileggi, Actionable Three-Phase Infeasibility Optimization with Varying Slack Sources, IEEE PES General Meeting, July 16-20, 2023.
S. (Cindy) Li, A. Pandey, B. Hooi, C. Faloutsos and L. Pileggi, “Dynamic Graph-Based Anomaly Detection in the Electrical Grid,” in IEEE Transactions on Power Systems, vol. 37, no. 5, pp. 3408-3422, Sept. 2022, doi: 10.1109/TPWRS.2021.3132852.
A. Agarwal, L. Pileggi, “Large Scale Multi-Period Optimal Power Flow with Energy Storage Systems Using Differential Dynamic Programming,” IEEE PES Transactions on Power Systems, 2021.
P. Donti, A. Agarwal, L. Pileggi, Z. Kolter, Adversarially Robust Learning for Security-Constrained Optimal Power Flow, Neural Information Processing Systems, 2021
T. McNamara, A. Pandey, A. Agarwal, L. Pileggi, Two-Stage Homotopy Method to Incorporate Discrete Control Variables into AC-OPF, Power Systems Computation Conference (PSCC), June 27-July 1, 2022
A. Agarwal, P. Donti, L. Pileggi, Employing Adversarial Robustness Techniques for Large-Scale Stochastic Optimal Power Flow, 22nd Power Systems Computation Conference (PSCC), Porto, Portugal, 2022
A. Agarwal, L. Pileggi, Efficient Steady State Analysis of the Grid Using Electromagnetic Transient Models, 22nd Power Systems Computation Conference (PSCC), Porto, Portugal, 2022.
E. Foster, A. Pandey, L. Pileggi, Three-Phase Infeasibility Analysis for Distribution Grid Studies, Power Systems Computation Conference (PSCC), June 27-July 1, 2022.
Agarwal, L. Pileggi, “Large Scale Multi-Period Optimal Power Flow with Energy Storage Systems Using Differential Dynamic Programming,” IEEE PES Transactions on Power Systems, 2021.
(Cindy) Li, A. Pandey, B. Hooi, C. Faloutsos, and L. Pileggi, “Dynamic Graph-Based Anomaly Detection in the Electrical Grid,” IEEE Transactions on Power Systems, doi: 10.1109/TPWRS.2021.31328
A. Agarwal, A. Pandey and L. Pileggi, Fast AC Steady-State Power Grid Simulation and Optimization Using Prior Knowledge, (Best Paper Award) IEEE PES General Meeting, July 25-29, 2021.
S. (Cindy) Li, A. Pandey, and L. Pileggi, A WLAV-based Robust Hybrid State Estimation using Circuit-theoretic Approach, (Best Paper Session) IEEE PES General Meeting, July 25-29, 2021.
N. T. Bandele, A. Pandey and L. Pileggi, Analytical Inverter-Based Distributed Generator Model for Power Flow Analysis, IEEE PES General Meeting, July 25-29, 2021.
A. Pandey, A. Agarwal, L. Pileggi, “Incremental Model Building Homotopy Approach for Solving Exact AC-Constrained Optimal Power Flow,” Hawaii International Conference on System Sciences-54, Hawaii, 2021.
S. Li, A. Pandey, S. Kar, L. Pileggi, “A Circuit-Theoretic Approach to State Estimation,” IEEE PES Innovative Smart Grid Technologies Europe (ISGT-Europe), October 2020.
S. Li, A. Pandey, and L. Pileggi, “A LASSO-Inspired Approach for Localizing Power System Infeasibility,” IEEE PES General Meeting, Montreal, Canada, August 2020.
A. Agrawal, A. Pandey, and L. Pileggi, Robust Event-Driven Dynamic Simulation using Power Flow, IEEE Power Systems Computation Conference (PSSC), June 2020.
Jovicic, M. Jereminov, L. Pileggi, Gabriela Hug, Enhanced Modelling Framework for Equivalent Circuit-Based Power System State Estimation, IEEE Transactions on Power Systems, February 2020 (10.1109/TPWRS.2020.2974459).
Jereminov, D.M. Bromberg, A. Pandey, M.R. Wagner, and L. Pileggi, “Evaluating Feasibility within Power Flow,” IEEE Transactions on Smart Grid, Vol. 11, No. 4, July 2020. DOI: 10.1109/TSG.2020.2966930.
A. Pandey and L. Pileggi, “Steady-State Simulation for Combined Transmission and Distribution Systems,” in IEEE Transactions on Smart Grid, Vol 11, Issue 2, March 2020. (DOI: 10.1109/TSG.2019.2932403).
A. Pandey and L. Pileggi, “Steady-State Simulation for Combined Transmission and Distribution Systems,” in IEEE Transactions on Smart Grid, August 2019. (DOI: 10.1109/TSG.2019.2932403)
A. Jovicic, M. Jereminov, L. Pileggi, G. Hug, “A Linear Formulation for Power System State Estimation including RTU and PMU Measurements,” IEEE PES Innovative Smart Grid Technologies Europe Conference, 2019.
A. Pandey, A. Agarwal, M. Jereminov, M.R. Wagner, D.M. Bromberg, L. Pileggi, “Robust Sequential Steady-State Analysis of Cascading Outages,” IEEE PES Innovative Smart Grid Technologies Europe Conference, 2019.
A. Agarwal, A. Pandey, M. Jereminov, L. Pileggi, “Implicitly Modeling Frequency Control with Power Flow,” IEEE PES Innovative Smart Grid Technologies Europe Conference, 2019.
A. Pandey, A. Agarwal, M. Jereminov, B. Rawn, T. Nwachuku and L. Pileggi, “Improving Voltage Profile of the Nigerian Power Grid,” in Proc. IEEE PES/IAS PowerAfrica Conference, Abuja Nigeria, August 2019.
M. Jereminov, A. Terzakis, M. Wagner, A. Pandey, L. Pileggi, “Robust and Efficient Power Flow Convergence with G-min Stepping Homotopy Method,” in Proc. IEEE Conference on Environment, Electrical Engineering and I&CPS Europe, Genoa, Italy, June 2019.
M. R. Wagner, M. Jereminov, A. Pandey, and L. Pileggi, “A Probabilistic Approach to Power System State Estimation using a Linear Algorithm,” in 2019 IEEE Conference on Environment and Electrical Engineering and I&CPS Europe, 2019.
M. Jereminov, A. Jovicic, M. Wagner, G. Hug, L. Pileggi, “Equivalent Circuit Programming for Estimating the State of a Power System,” in Proc. IEEE PowerTech Milan, June 2019.
M. R. Wagner, M. Jereminov, A. Pandey, and L. Pileggi, “A Probabilistic Approach to Power System State Estimation using a Linear Algorithm,” in 2019 IEEE Conference on Environment and Electrical Engineering and I&CPS Europe, 2019.
A. Pandey, M. Jereminov, M. R. Wagner, D. M. Bromberg, G. Hug, L. Pileggi, Robust Power Flow and Three Phase Power Flow Analyses, IEEE Transactions on Power Systems, Vol. 34, Issue:1, pp. 616-626, January 2019.
M. Jereminov, B. Hooi, A. Pandey, H. Song, C. Faloutsos and L. Pileggi, “Impact of Load Models on Power Flow Optimization,” IEEE PES General Meeting, Atlanta, GA, August 2019.
M. Jereminov, A. Pandey, L. Pileggi, Equivalent Circuit Formulation for Solving AC Optimal Power Flow, IEEE Transactions on Power Systems, December 2018.
B. Hooi, D. Eswaran, A. Pandey, M. Jereminov, L. Pileggi, and C. Faloutsos, “ChangeDAR: Online Localized Change Detection for Sensor Data on a Graph,” (Best Student Paper Award, Runner Up), Proceedings of the 2018 ACM Conference on Information and Knowledge Management, 2018.
A. Jovicic, M. Jeremino, L. Pileggi and G. Hug, “An Equivalent Circuit Formulation for Power System State Estimation including PMUs,” (Best Paper Award, Second Prize), 50th North American Power Symposium, October 2018.
B. Hooi, D. Eswaran, H.A. Song, A. Pandey, M. Jereminov, L. Pileggi, and C. Faloutsos. “GridWatch: Sensor Placement and Anomaly Detection in the Electrical Grid,” European Conference on Machine Learning and Principles and Practice of Knowledge Discovery in Databases (ECML-PKDD) 2018.
A. Pandey, M. Jereminov, M. Wagner, G. Hug, and L. Pileggi, “Robust Convergence of Power Flow using Tx Stepping Method with Equivalent Circuit Formulation, Power Systems Computation Conference”, June 2018.
Sadi, F., Sweeney, J., McMillan, S., Low, T. M., Hoe, J., Pileggi, L., & Franchetti, F., “PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV”. HPEC: High Performance Embedded Computing Annual Workshop(2018).
M.R. Wagner, A. Pandey, M. Jereminov, and L. Pileggi. Robust Probabilistic Analysis of Transmission Power Systems based on Equivalent Circuit Formulation, Proceedings of the International Conference on Probabilistic Methods Applied to Power Systems, June 2018.
B. Hooi, H.A. Song, A. Pandey, M. Jereminov, L. Pileggi, and Christos Faloutsos. StreamCast: Fast and Online Mining of Power Grid Time Sequences. Proceedings of the 2018 SIAM.
H.A. Song, B. Hooi, A. Pandey, M. Jereminov, L. Pileggi, C. Faloutsos, “PowerCast: Mining and Forecasting Power Grid Sequences”, ECML-PKDD 2017 Conference, September 2017.
M. Jereminov, A. Pandey, H.A. Song, B. Hooi, C. Faloutsos, L. Pileggi, “Linear Load Model for Robust Power System Analysis”, IEEE PES Integrative Smart Grid Technologies Europe, September 2017.
A. Pandey, M. Jereminov, G. Hug, and L. Pileggi, “Improving Power Flow Robustness via Circuit Simulation Methods”, IEEE PES General Meeting, (Prize Paper Award), July 2017.
A. Pandey, M. Jereminov, X. Li, G. Hug, L. Pileggi, “Aggregated Load and Generation Equivalent Circuit Models with Semi-Empirical Data Fitting”, IEEE Green Energy and Systems Conference (IGESC 2016), November 2016.
M. Jereminov, A. Pandey, G. Hug, X. Li and L. Pileggi, “Steady-State Analysis of Power System Harmonics Using Equivalent Split-Circuit Models”, IEEE PES Integrative Smart Grid Technologies Europe, October 2016.
A. Pandey, M. Jereminov, G. Hug, X. Li and L. Pileggi, “Unified Power System Analyses and Models using Equivalent Circuit Formulation”, IEEE PES Innovative Smart Grid Technologies Conference, September 2016.
M. Jereminov, D. Bromberg, A. Pandey, G. Hug, X. Li and L. Pileggi, “An Equivalent Circuit Formulation for Three-Phase Power Flow Analysis of Distribution Systems” IEEE PES Transmission and Distribution Conference, Dallas, Texas, May 2016.
M. Jereminov, D. Bromberg, X. Li, G. Hug and L. Pileggi, “Improving Robustness and Modeling Generality for Power Flow Analysis” IEEE PES Transmission and Distribution Conference, Dallas, Texas, May 2016.
X. Chen, D. Bromberg, G. Hug, X. Li and L. Pileggi, ” A Robust and Efficient Power Series Method for Tracing PV Curves”, The 47th North American Power Symposium, October 2015.
D. Bromberg, G. Hug, X. Li and L. Pileggi, “An Equivalent Circuit Formulation of the Power Flow Problem with Current and Voltage State Variables”,Powertech Eindhoven, June 2015.
Xun Yang, Byron Krauter and L. Pileggi, “Combined ac and Transient Power Distribution Analysis”, Proceedings of the Custom Integrated Circuits Conference, May 1996.
C. Talbot, Deepali Garg, L. Pileggi and K. Mai, “An IP-Agnostic Foundational Cell Array Offering Supply Chain Security,” The 61st Design Automation Conference, June 2024.
C. Talbot, Deepali Garg, L. Pileggi and K. Mai, “IP-Agnostic Standard Cell Fabric Offering Tamper Resistance and Supply Chain Resilience,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 2024.
D. Garg, J. Sweeney and L. Pileggi, Quantifying the Efficacy of Logic Locking Methods, International Conference on VLSI Design, Kolkata India, January 2024.
D. Garg, J. Sweeney and L. Pileggi, Quantifying the Efficacy of Logic Locking Methods, International Conference on VLSI Design, Kolkata India, January 2024.
B. Singer, A. Pandey, S. Li, L. Bauer, C. Miller, L. Pileggi, V. Sekar, Shedding Light on Inconsistencies in Grid Cybersecurity: Disconnects and Recommendations, IEEE Symposium on Security and Privacy, May 22-26, 2023.
P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Top-Down Synthesis of Soft eFPGA Fabrics Using Standard ASIC Flows,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 29-April 1, 2021.
S. Pagliarini, J. Sweeney, K. Mai, S. Blanton, S. Mitra and L. Pileggi, “Split-Chip Design to prevent IP Reverse Engineering,” in IEEE Design & Test, doi: 10.1109/MDAT.2020.3033255.
P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Top-down physical design of soft embedded FPGA fabrics,” In proceedings of FPGA conference, Feb-March 2021.
P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Hardware Redaction via Designer-Directed Fine-Grained Soft eFPGA Insertion,” In proceedings of Design and Test in Europe (DATE), February 1-5, 2021.
J. Sweeney, M.J.H. Heule, L. Pileggi, “Modeling Techniques for Logic Locking,” IEEE International Conference on Computer-Aided Design, November 2020.
Sweeney, M. J. H. Heule, and L. Pileggi. “Sensitivity Analysis of Locked Circuits,” 23rd International Conference on Logic for Programming, Artificial Intelligence and Reasoning (LPAR-23), May 2020.
I. Karageorgos, M. Isgenc, S. Pagliarini, and L. Pileggi, Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography, Journal of Hardware and Systems Security, November 2019 (DOI: 10.1007/s41635-019-00080-y).
J. Sweeney, M. Zackriya, S. Pagliarini, and L. Pileggi, “Latch-Based Logic Locking,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2020.
J. Sweeney, M. Zackriya, S. Pagliarini, and L. Pileggi, “Latch-Based Logic Locking,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 2020.
I. Karageorgos, M. Isgenc, S. Pagliarini, and L. Pileggi, Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography, Journal of Hardware and Systems Security, (DOI: 10.1007/s41635-019-00080-y).
J. Sweeney, M. Zackriya, S. Pagliarini and L. Pileggi, Securing Digital Systems via Split-Chip Obfuscation, GOMACTech Technical Program, March 2019.
K. Vaidyanathan, R. Liu, E. Sumbul, Q. Zhu, F. Franchetti, L. Pileggi, “Efficient and Secure Intellectual Property (IP) Design with Split Fabrication”, Hardware-Oriented Security and Trust, May 2014.
K. Vaidyanathan, B. P. Das, E. Sumbul, R. Liu, L. Pileggi, “Building Trusted ICs using Split Fabrication”, Hardware-Oriented Security and Trust, May 2014.
K. Vaidyanathan, B. Prasad Das, L. Pileggi, “Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack”, IEEE/ACM Design Automation Conference, June 2014.
J. Tao, Y-C. Wang, M. Jun, X. Li, R. Negi, T. Mukherjee and L. Pileggi, “Efficient System-Level Performance Modeling and Optimization for Reprogrammable Radio Frequency (RF) Systems”, Frontiers in Analog CAD Workshop, February 2013.
Y.-C. Wang, S. Yin, M. Jun, X. Li, L. Pileggi, T. Mukherjee, R. Negi, “Accurate Passivity-Enforced Macromodeling for RF Circuits via Iterative Zero/Pole Update Based on Measurement Data”, 20th Asia and South Pacific Design Automation Conference (ASP-DAC), 2015.
K. Vaidyanathan, R. Liu, L. Liebmann, K. Lai, A. Strojwas, L. Pileggi, “Design Implications of Extremely Restricted Patterning”, Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol 13 (03), 2014.
M. Jun, R. Negi, Y.-C. Wang, T. Mukherjee, X. Li, J. Tao, and L. Pileggi, “Joint Invariant Estimation of RF impairments for Reconfigurable Radio Frequency(RF) Front-end”, Globecom Workshop – Emerging Technologies for 5G Wireless Cellular Networks, 2014.
Minhee Jun, Jun Tao, Ying-Chih Wang, Shihui Yin, Rohit Negi, Xin Li, Tamal Mukherjee and Lawrence Pileggi, “Environment-adaptable efficient optimization for programming of reconfigurable radio frequency (RF) receivers”, IEEE Military Communications Conference (MILCOM), 2014.
F. Sadi, B. Akin, D. Popovici, J. Hoe, L. Pileggi, F. Franchetti, “Algorithm/Hardware Co-optimized SAR Image Reconstruction with 3D-stacked Logic in Memory”, Eighteenth Annual High Performance Embedded Computing (HPEC) Workshop at MIT Lincoln Laboratory, September 2014.
K. Vaidyanathan, L. Liebmann, A. Strojwas, L. Pileggi, “Sub-20 nm Design Technology Co-Optimization for Standard Cell Logic”, Int’l Conference on Computer-Aided Design, November 2014.
J. Tao, Y.-C. Wang, M. Jun, X. Li, R. Negi, T. Mukherjee, L. Pileggi, “Toward Efficient Programming of Reconfigurable Radio Frequency (RF) Receivers”, 19th Asia and South Pacific Design Automation Conference (ASP-DAC), January 2014.
S. Sun, F. Wang, S. Yaldiz, X. Li, L. Pileggi, A. Natarajan, M. Ferriss, J. Plouchart, B. Sadhu, B. Parker, A. Valdes-Garcia, M. Sanduleanu, J. Tierno, D. Friedman, “Indirect Performance Sensing for On-Chip Analog Self-Healing via Bayesian Model Fusion”, Int’l Custom Integrated Circuits Conference, September 2013.
E. Sumbul, A. Patterson, G. Fedder, F. Franchetti, G. Piazza and L. Pileggi, “Trusted Split-Fabrication System-on-Chip Design Technology and Methodology”, (Invited Paper) GOMACTech Technical Program, March 2013.
Q. Zhu, C. Berger, E. Turner, L. Pileggi and F. Franchetti, “Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation”, Journal of Signal Processing Systems, 2012.
Q. Zhu, L. Pileggi and F. Franchetti, “Smart Memory Synthesis for Energy-Efficient Computed Tomography Reconstruction”, Proceedings of the SRC Techcon Conference, September 2012.
Q. Zhu, K. Vaidyanathan, O. Shacham, M. Horowitz, L. Pileggi and F. Franchetti, “Design Automation Framework for Application-Specific Logic-in-Memory Blocks”, IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2012.
F. Wang, G. Keskin, A. Phelps, J. Rotner, X. Li, G. Fedder, T. Mukherjee and L. Pileggi, “Statistical Design and Optimization for Adaptive Post-Silicon Tuning of MEMS Filters”, IEEE/ACM Design Automation Conference (DAC), 2012.
K. Vaidyanathan, S.H. NG, D. Morris, N. Lafferty, L. Liebmann, W. Huang, K. Lai, L. Pileggi, A.J. Strojwas, “Design and Manufacturability Tradeoffs in Unidirectional & Bidirectional Standard Cell Images in 14 nm”, SPIE Advanced Lithography Conference, February 2012.
W. Huang, D. Morris, N. Lafferty, L. Liebmann, K. Vaidyanathan, K. Lai, L. Pileggi, A.J. Strojwas, “Local Loops for Robust Inter-Layer Routing at Sub-20 nm Nodes”, SPIE Advanced Lithography Conference, February 2012.
M. Althoff, A. Rajhans, B. Krogh, S. Yaldiz, X. Li, and L. Pileggi, “Formal Verification of Phase-Locked Loops Using Reachability Analysis and Continuization”, Communications of the ACM (invited paper), 2012.
M. Althoff, A. Rajhans, B. Krogh, S. Yaldiz, X. Li and L. Pileggi, “Formal Verification of Phase-Locked Loops Using Reachability Analysis and Continuization”, Int’l Conference on Computer-Aided Design (Best Paper Award), November 2011.
C.-Y. Wen, J. Paramesh, L. T. Pileggi, J. Li, S. Kim, J. Proesel, C. Lam, “Post-Silicon Calibration of Analog CMOS Using Phase-Change Memory Cells”, European Solid-State Device Research Conference (ESSDERC), September 2011.
M. Althoff, A. Rajhans, B.H. Krogh, S. Yaldiz, X. Li, L. Pileggi, “Using Continuization in Reachability Analysis for the Verification of a Phase-Locked Loop”, In Proc. Frontiers in Analog Circuit (FAC) Synthesis and Verification, July 2011.
D. Morris, K. Vaidyanathan and L. Pileggi, “Design Without Rules: A Pattern Construct Methodology”, Proceedings of the SRC Techcon Conference, September 2011.
D. Morris, K. Vaidyanathan, N. Lafferty, K. Lai, L. Liebmann, L. Pileggi, “Design of Embedded Memory and Logic Based On Pattern Constructs”, IEEE Symposium on VLSI (Invited Presentation), June 2011.
S. Yaldiz, F. Wang, X. Li, L. Pileggi, A.S. Natarajan, M.A. Ferriss, J. Tierno, “Virtual Phase Noise Sensor for Self-Healing Voltage Controlled Oscillators”, GOMACTech-11 Technical Program, March 2011.
V. Rovner, T. Jhaveri, Daniel Morris, Andrzej J. Strojwas, and Larry Pileggi, “Performance and Manufacturability Trade-offs of Pattern Minimization for sub-22nm Technology Nodes”, SPIE Advanced Lithography Conference, February 2011.
A. Bonnoit, S. Herbert and L. Pileggi, “Reducing Variability in Chip-Multiprocessors with Adaptive Body Biasing”, International Symposium on Low Power Electronics and Design, August 2010.
G. Keskin, J. Proesel and L. Pileggi, “Statistical Modeling and Post Manufacturing Configuration for Scaled Analog CMOS”, Int’l Custom Integrated Circuits Conference, Sept. 2010.
G. Keskin, J. Proesel and L. Pileggi, “Modeling of Statistical Element Selection Based Self-Healing Analog Circuits”, Proceedings of the SRC Techcon Conference, September 2010.
D. Morris, S. Rovner, L. Pileggi, A. Strojwas and K. Vaidyanathan, “Enabling Application-Specific Integrated Circuits on Limited Pattern Constructs”, IEEE Symposium on VLSI (Invited Presentation), June 2010.
Tejas Jhaveri, Vyacheslav Rovner, Lars Liebmann, Larry Pileggi, Andrzej Strojwas, Jason D. Hibbeler, “Design Technology Co-optimization for Predictive Technology Scaling Beyond Gratings, Invited Keynote Paper”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 4, April 2010.
T. Jhaveri, U. Urslan, V. Rovner, L. Pileggi & A. J. Strojwas, “Application of the Cost-Per-Good-Die Metric for Process-Design Co-optimization”, SPIE Advanced Lithography Conference, Selected for Keynote Presentation, February 2010.
L. Liebmann, J. Hibbeler, N. Hieter, L. Pileggi, M. Moe, T. Jhaveri, V. Rovner, “Demonstrating the benefits of template-based design-technology co-optimization”, SPIE Advanced Lithography Conference, February 2010.
A. Bonnoit, S. Herbert, L. Pileggi and D. Marculescu, “Integrating Dynamic Voltage/Frequency Scaling and Adaptive Body Biasing using Test-time Voltage Selection”, International Symposium on Low Power Electronics and Design, August 2009.
T. Jhaveri, A. J. Strojwas, L. Pileggi and V. Rovner, “Economic Assessment of Lithography Strategies for the 22nm Technology Node”, Proceedings of the SPIE/BACUS Symposium on Photomask Technology, September 2009.
B. Taylor, D. Morris and L. Pileggi, “Fixed Depth Reasoning in Satisfiability and its Applications to Combinatorial Optimization”, Proceedings of the SRC Techcon Conference, September 2009.
J. Wang, S. Yaldiz, X. Li and L. Pileggi, “SRAM Parametric Failure Analysis, Proceedings of ACM/IEEE Design Automation Conference”, June 2009.
A. J. Strojwas, T. Jhaveri, V. Rovner and L. Pileggi, “Creating an Affordable 22nm Node using Design-Lithography Co-Optimization”, Proceedings of ACM/IEEE Design Automation Conference, June 2009.
S. Yaldiz, U. Arslan, X. Li and L. Pileggi, “Efficient Statistical Analysis of Read Timing Failures in SRAM Circuits”, IEEE Int’l Symposium on Quality in Electronic Design, March 2009.
Tejas Jhaveri, Andrzej Strojwas, Larry Pileggi & Vyacheslav Rovner, “OPC Simplification & Mask Cost Reduction using Regular Design Fabrics”, SPIE Advanced Lithography Conference, February 2009.
Lars Liebmann, Larry Pileggi, Jason Hibbeler, Vyacheslav Rovner, Tejas Jhaveri, Greg Northrop, “Simplify to Survive: Prescriptive Layouts Ensure Profitable Scaling to 32nm and Beyond”, SPIE Advanced Lithography Conference, February 2009.
Bin Wan, Jian Wang, Gokce Keskin, and Lawrence T. Pileggi, “Ring Oscillators for Single Process-Parameter Monitoring”, IEEE Workshop on Test Structure Design for Variability Characterization, November 2008.
L. Pileggi, G. Keskin, X. Li, K. Mai and J. Proesel, “Mismatch Analysis and Statistical Design at 65 nm and Below”, Invited Paper, Int’l Custom Integrated Circuits Conference, Sept. 2008.
G. Keskin, L. Pileggi, X. Li and K. Mai, “Process Variation Effects on Input Offset Voltage of CMOS SRAM Sense Amplifiers”, Proceedings of the SRC Techcon Conference, September 2008.
Xin Li, Jiayong Le, Mustafa Celik and Lawrence Pileggi, “Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 6, pp. 1041-1054, June 2008.
E. Small, S.M. Sadeghipour, L. Pileggi, M. Asheghi, “Thermal Analyses of Confined Cell Design for Phase Change Random Access Memory (PCRAM)”, ITherm, May 2008.
Xin Li, Yaping Zhan and Lawrence Pileggi, “Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 5, pp. 831-843, May 2008.
T. Jhaveri, A.J. Strojwas, L. Pileggi, V. Rovner, “Enabling Technology Scaling with ‘In Production’ Lithography Processes”, SPIE Advanced Lithography Conference, February 2008.
J. Brown, B. Taylor, R. D. Blanton, and L. Pileggi, “Automated Testability Enhancements for Logic Brick Libraries”, Proceedings of Design and Test Europe, March 2008.
Benton Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence Pileggi, Rob Rutenbar and Kenneth Shepard, “Digital circuit design challenges and opportunities in the era of nanoscale CMOS”, Proceedings of The IEEE (PTI), vol. 96, no. 2, pp. 343-365, February 2008.
B. Taylor and L. Pileggi, “Exact Methods for Physical Design of Regular Logic Bricks”, Proceedings of the SRC Techcon Conference, October 2007.
X. Li, B. Taylor, Y-T. Chen and L. Pileggi, “Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization” , Proceedings of the International Conference on Computer-Aided Design, November 2007.
B.Taylor and L. Pileggi, “Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks”, Proceedings of ACM/IEEE Design Automation Conference, June 2007.
J. Wang, X. Li and L. Pileggi, “Parameterized Macromodeling for Analog System-Level Design Exploration”, Proceedings of ACM/IEEE Design Automation Conference, June 2007.
K. Yu, S. Wang, A. Gerdemann, C. Weldon, D. Reber, J. Vasek, S. Veeraraghavan, V. Rovner, T. Jhaveri, T. Hersan, L. Pileggi”,Regular Layout Performance Dependence on Cell Abutment”, Joint Conference on Design For Manufacturing, June 2007.
Xin Li, Padmini Gopalakrishnan, Yang Xu and Lawrence Pilegg, “Robust analog/RF circuit design with projection-based performance modeling”, IEEE Trans. on Computer-Aided Design of Integrated Circuits (TCAD), January 2007.
Xin Li, Jiayong Le, Padmini Gopalakrishnan and Lawrence Pileggi, “Asymptotic probability extraction for non-Normal performance distributions”, IEEE Trans. on Computer-Aided Design of Integrated Circuits (TCAD), January 2007.
Tejas Jhaveri, Vyacheslav Rovner, Larry Pileggi, Andrzej J. Strojwas, et al., “Maximization of Layout Printability/Manufacturability by Extreme Layout Regularity”, Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol 6 (03), January 2007.
Xin Li, Jiayong Le, Lawrence Pileggi, “Statistical Performance Modeling and Optimization”, Foundations and Trends in Electronic Design Automation: Vol. 1: No 4, pp 331-480, January 2007.
K.Y. Tong, V. Rovner, L. Pileggi and V. Kheterpal, “Design Methodology of Regular Logic Bricks for Robust Integrated Circuits”, Int’l Conference on Computer Design, October 2006.
G. Keskin, X. Li and L. Pileggi, “Active On-Die Suppression of Power Supply Noise”, Int’l Custom Integrated Circuits Conference, Sept. 2006.
P. Li, L. Pileggi, M. Ashegi, R. Chandra, “Efficient Full-Chip Thermal Modeling and Analysis”, IEEE Transactions on CAD, Vol. 25, Issue 9, pp. 1763 – 1776, Sept. 2006.
X. Li, J. Le and L. Pileggi, “Projection-Based Statistical Analysis of Full-Chip Leakage Power with Non-Log-Normal Distributions”, Design Automation Conference, June 2006.
P. Gopalakrishnan, X. Li and L. Pileggi, “A Metric-Embedding Inspired Approach to Timing-driven FPGA Placement”, Design Automation Conference, June 2006.
L. Pileggi and A.J. Strojwas, “Regular Fabrics for Nano-Scaled CMOS Technologies”, International Solid State Circuits Conference (invited presentation), February 2006.
T. Jhaveri, L. Pileggi, V. Rovner, A.J. Strojwas, “Maximization of layout printability/manufacturability by extreme layout regularity”, SPIE 31st International Symposium on Microlithography Symposium (invited presentation), February 2006.
X. Li, J. Wang, W. Chiang and L. Pileggi, “Performance-Centering Optimization for System-Level Analog Design Exploration”, Proceedings of the International Conference on Computer-Aided Design, November 2005.
X. Li, P. Li and L. Pileggi, “Parameterized Interconnect Order Reduction with Explicit-and-Implicit Multi-Parameter Moment Matching for Inter/Intra-Die Variations”, Proceedings of the International Conference on Computer-Aided Design, November 2005.
X. Li, J. Le, M. Celik and L. Pileggi, “Defining Statistical Sensitivity for Timing Optimization of Logic Circuits with Large-Scale Process and Environmental Variations”, Proceedings of the International Conference on Computer-Aided Design, November 2005.
X. Li, J. Le, L. Pileggi and A.J. Strojwas, “Projection-Based Performance Modeling for Inter/Intra-Die Variations”, Proceedings of the International Conference on Computer-Aided Design, November 2005.
G. Keskin, X. Li and L. Pileggi, “Reducing Power Supply Noise in Integrated Circuits Using Active Resistors”, Proceedings of the SRC Techcon Conference, October 2005.
R. Batra, P. Li, L. Pileggi, W.J. Chiang, “A Behavioral Level Approach for Nonlinear Dynamic Modeling of Voltage-Controlled Oscillators”, Int’l Custom Integrated Circuits Conference, Sept. 2005.
P. Li, Y. Dong and L. Pileggi, “Temperature-Dependent Optimization of Cache Leakage Power Dissipation”, Proceedings of the International Conference on Computer Design, October 2005.
P. Gopalakrishnan and L. Pileggi, “Timing Driven Initial Placement for FPGAs via Graph Matching”, Proceedings of the SRC Techcon Conference, October 2005.
V. Kheterpal, T. Hersan, V. Rovner, D. Motiani, Y. Takagawa, L. Pileggi and A. Strojwas, “Design Methodology for IC Manufacturability Based on Regular Logic-Bricks”, Design Automation Conference, June 2005.
Y. Zhan, X. Li, A. Strojwas, and L. Pileggi, “Correlation-Aware Statistical Timing Analysis with Non-Gaussian Delay Distributions”, Design Automation Conference, June 2005.
Y. Xu, K. L. Hsiung, L. Pileggi, and S. Boyd, “OPERA: OPtimization with Ellipsoidal uncertainty for Robust Analog IC design”, Design Automation Conference, June 2005.
X. Li, K.Y. Tong, Y. Xu and L. Pileggi, “Robust Optimization for Radiation Hardened Analog/RF Circuits”, GOMACTech-05 Technical Program, April 2005.
Y. Xu and L. Pileggi, “Metal-mask Configurable RF Integrated Circuits”, GOMACTech-05 Technical Program, April 2005.
S. Biswas, P. Li, S. Blanton and L. Pileggi, “Specification Test Compaction for Analog Circuits and MEMS”, Design and Test in Europe Conference (DATE), February 2005.
P. Li and L. Pileggi, “Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction”, Design and Test in Europe Conference (DATE), February 2005.
P. Li and L. T. Pileggi, “Compact Reduced-Order Modeling of Weakly Nonlinear Analog and RF Circuits”, IEEE Transactions on Computer-Aided Design, Vol. 23, No. 2, pp. 184-203, February 2005.
R. Batra, P. Li, Y-T. Chen and L. Pileggi, “A Methodology for Analog Circuit Macromodeling”, IEEE International Workshop on Behavioral Modeling and Simulation, October 2004.
R. Marculescu, D. Marculescu and L. Pileggi, “Toward an Integrated Design Methodology Fault Tolerant”, Multiple Clock/Voltage Integrated Systems, Proceedings of the International Conference on Computer Design, October 2004.
X. Li, J. Le, P. Gopalakrishnan and L. Pileggi, “Asymptotic Probability Extraction for Non-Normal Distributions of Circuit Performance”, Proceedings of the International Conference on Computer-Aided Design (Best Paper Award), November 2004.
X. Li and L. Pileggi, “Robust Analog/RF Circuit Design with Projection-Based Posynomial”, Proceedings of the International Conference on Computer-Aided Design, November 2004.
P. Li and L. Pileggi, “Efficient Harmonic Balance Simulation Using Multi-Level Frequency Decomposition”, Proceedings of the International Conference on Computer-Aided Design, November 2004.
P. Li, L. Pileggi, M. Ashegi, R. Chandra, “Efficient Full-Chip Thermal Modeling and Analysis”, Proceedings of the International Conference on Computer-Aided Design, November 2004.
V. Chandra, H. Schmit and L. Pileggi, “A Power Aware System Level Interconnect Design Methodology for Latency-Insensitive”, Proceedings of the International Conference on Computer-Aided Design, November 2004.
Yang Xu, Larry Pileggi, Stephan Boyd, “ORACLE: Optimization with Recourse of Analog Circuits including Layout Extraction”, August 2004
Xin Li, Yang Xu, Peng Li, Padmini Gopalakrishnan and Lawrence Pileggi, “A Frequency Relaxation Approach for Analog/RF System-Level Simulation”, ACM/IEEE Design Automation Conference, June 2004.
Yang Xu, Larry Pileggi, Stephan Boyd, “ORACLE: Optimization with Recourse of Analog Circuits including Layout Extration”, ACM/IEEE Design Automation Conference, June 2004.
Jiayong Le, Xin Li and Larry Pileggi, “STAC: Statistical Timing Analysis with Correlation”, ACM/IEEE Design Automation Conference, June 2004.
Veerbhan Kheterpal, Andrzej Strojwas, Larry Pileggi, “Routing Architecture Exploration for Regular Fabrics”, ACM/IEEE Design Automation Conference, June 2004.
Satrajit Gupta and Larry Pileggi, “Hierarchical Modeling of Magnetic Coupling”, ACM/IEEE Design Automation Conference, June 2004.
Y. Xu, C. Boone and L. Pileggi, “Metal-mask configurable RF Front-end Circuits”, in Proceedings of IEEE RFIC Symposium, June 2004.
L. Pileggi and A.J. Strojwas, Exploring Regular Fabrics to Optimize the Performance-Cost Trade-Off, International Solid State Circuits Conference (invited presentation), February 2004.
V. Chandra, A. Xu, H. Schmit and L. Pileggi, “An Interconnect Channel Design Methodology for High Performance Integrated Circuits”, Design and Test in Europe Conference (DATE), February 2004.
M. Beattie and L.T. Pileggi, “Parasitic Extraction with Multipole Refinement”, IEEE Transactions on Computer-Aided Design, Vol. 23, (5 pages), February 2004.
P. Li and L. T. Pileggi, “Efficient Per-Nonlinearity Distortion Analysis for Analog and RF Circuits”, IEEE Transactions on Computer-Aided Design, Vol. 22, No. 10, pp. 1297-1309, October 2003.
H. Zheng, B. Krauter and L.T. Pileggi, “Electrical Modeling of Integrated-Package Power/Ground Distributions”, IEEE Design and Test, Volume: 20 Issue: 3, pp. 23-31, May-June 2003.
P. Li and L. Pileggi, “Modeling Nonlinear Communication ICs Using a Multivariate Formulation”, IEEE International Workshop on Behavioral Modeling and Simulation, October 2003.
P. Li, X. Li, Y. Xu and L. Pileggi, “A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits”, Proceedings of the International Conference on Computer-Aided Design, November 2003.
J. Le, A. Devgan and L. Pileggi, “Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics”, Proceedings of the International Conference on Computer-Aided Design, November 2003.
S. Gupta and L. Pileggi, “Hierarchical Modeling of Electrostatic and Magnetostatic Coupling”, Proceedings of the SRC Techcon Conference, August 2003.
X. Qi, G. Leonhardt, D. Flees, X-D, Yang, S. Kim, S. Mueller, H. Mau and L. Pileggi, “Simulation Approach for Inductance Effects of VLSI Interconnects”, In Proc. of the Great Lakes Symposium on VLSI, May 2003.
D. Pandini, L. Pileggi, A. Strojwas, “Bounding the Efforts on Congestion Optimization for Physical Synthesis”, In Proc. of the Great Lakes Symposium on VLSI, May 2003.
I. Bolsens, A. Broom, C. Hamlin, P. Magarshack, Z. Or-Bach and L. Pileggi, Fast, “Cheap and Under Control: The Next Implementation Fabric”, IEEE/ACM Design Automation Conference, June 2003.
L. Pileggi, H. Schmit, A.J. Strojwas, et al, “Exploring Regular Fabrics to Optimize the Performance-Cost Trade-Off”, IEEE/ACM Design Automation Conference, June 2003.
X. Li, P. Li, Y. Xu and L. Pileggi, “Analog and RF Circuits Macromodels for System-Level Analysis”, IEEE/ACM Design Automation Conference, June 2003.
P. Li and L. Pileggi, “NORM: Compact Model Order Reduction of Weakly Nonlinear Systems”, IEEE/ACM Design Automation Conference (Best Paper Award), June 2003.
C. Patel, A. Cozzie, H. Schmit and L. Pileggi, “An Architecture Exploration of Via Patterned Gate Arrays”, Internation Symposium on Physical Design, April 2003.
E. Malley, A. Salinas, K. Ismail and L. Pileggi, “Power Comparison of Throughput Optimized IC Busses”, IEEE Symposium on VLSI, February 2003.
Y. Xu and L. Pileggi, “Noise Macromodel for Radio Frequency Integrated Circuits”, Design and Test in Europe Conference (DATE), March 2003.
D. Pandini, L. T. Pileggi and A.J. Strojwas, “Global and Local Congestion Optimization in Technology Mapping”, IEEE Transactions on Computer-Aided Design, Vol. 22, No. 4, pp. 498-506, April 2003.
P. Li and L. Pileggi, “Nonlinear Distortion Analysis Via Linear-Centric Models”, Asia- Pacific Design Automation Conference, February 2003.
X. Li and L. Pileggi, “A Frequency Separation Macromodel for System-Level Simulation of RF Circuits”, Asia-Pacific Design Automation Conference, February 2003.
M. Beattie and L.T. Pileggi, “On-Chip Induction Modeling: Basics and Advanced Methods”, Special Issue of IEEE Transactions on VLSI Systems, vol. 10, No. 6, pp. 712-729, December 2002.
M. Celik, H. Zheng and L. Pileggi, “Efficient Reduction of Susceptance-Based Package Models Using PRIMA”, Proceedings of the Topical Meeting on Electrical Performance of Electronic Packaging, October 2002.
T. Lin and L. Pileggi, “Throughput Driven IC Communication Synthesis”, Proceedings of the International Conference on Computer-Aided Design, November 2002.
H. Zheng and L. Pileggi, “Robust and Passive Model OrderReduction for Circuits Containing Susceptance Elements”, Proceedings of the International Conference on Computer-Aided Design, November 2002.
A. Koorapaty and L. Pileggi, Modular, “Fabric-specific Synthesis for Programmable Architectures”, International Conference on Field Programmable Logic and Applications, September 2002, France.
H. Zheng and L. Pileggi, “Modeling and Analysis of Regular Symmetrically Structured Power/Ground Distribution Networks”, ACM/IEEE Design Automation Conference, June 2002.
T. Lin, M. Beattie and L. Pileggi, “On the Efficacy of Simplified 2D On-Chip Inductance Models”, ACM/IEEE Design Automation Conference, June 2002.
E. Acar, F. Dartu and L. T. Pileggi, “TETA: Transistor level Waveform Evaluation for Timing Analysis”, IEEE Transactions on Computer-Aided Design, Vol. 21, No. 5, May 2002.
R. Arunachalam, R. D. Blanton, L. T. Pileggi, “Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation”, VLSI Design (Special Issue on TimingAnalysis and Optimization for DSM ICs), Vol.15, pp. 605-618, May 2002.
D. Pandini, L. Pileggi and A. Strojwas, “Understanding and Addressing the Impact of Wiring Congestion During Technology Mapping”, Int’l Symposium on Physical Design (ISPD), April 2002.
E. Acar, S. Nassif and L. Pileggi, “Time-Domain Simulation of Variational Interconnect Models”, Int’l Symposium on Quality in Electronic Design, March 2002.
H. Zhang, B. Krauter, M. Beattie and L. Pileggi, “Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses”, Design and Test in Europe Conference (DATE), March 2002.
E. Acar, L. Pileggi and S. Nassif, “A Linear-Centric Simulation Framework for Parametric Fluctuations”, Design and Test in Europe Conference (DATE), March 2002.
T. Lin, M. Beattie and L. Pileggi, “On-Chip Inductance Models:3D or not 3D?”, Design and Test in Europe Conference (DATE), March 2002.
P. Li and L. Pileggi, “A Linear-Centric Modeling Approach to Harmonic Balance Analysis”, Design and Test in Europe Conference (DATE), March 2002.
D. Pandini, L. Pileggi and A. Strojwas, “Congestion-Aware Logic Synthesis”, Design and Test in Europe Conference (DATE), March 2002.
P. Gopalakrishnan, A. Odabasioglu, L. T. Pileggi, and S. Raje, “Overcoming Wireload Model Uncertainty for Physical Design”, IEEE Transactions on Computer-Aided Design, Vol. 21, No. 1, January 2002.
M. Beattie, L. Pileggi, “Modeling Magnetic Coupling for Gigascale Interconnect”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
M. Beattie, L. Pileggi, “Inductance 101 (Embedded Tutorial)”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
R. Arunachalam, R. D. Blanton and L. Pileggi, “False coupling interactions in static timing analysis”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
Y-C. Lu, M. Celik, T. Young, and L. Pileggi, “Min/Max On-Chip Inductance Models and Delay Metrics”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
T. Lin and L. Pileggi, “RC(L)Interconnect Sizing With Second Order Considerations via Posynomial Programming”, Int’l Symposium on Physical Design (ISPD), April 2001.
P. Gopalakrishnan, A. Odabasioglu, L. Pileggi and S. Raje, “Overcoming Wireload Model Uncertainty During Physical Design”, Int’l Symposium on Physical Design (ISPD), April 2001.
Y. Liu, L. T. Pileggi and A.J. Strojwas, “ftd: Frequency to Time Domain Conversion for Reduced Order Interconnect Circuits”, IEEE Transactions on Circuits and Systems, April 2001.
M. Beattie and L. Pileggi, “Efficient Inductance Extraction via Windowing”, Design and Test in Europe Conference (DATE), March 2001.
E. Acar, S. Nassif and L. Pileggi, Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations, Int’l Symposium on Quality in Electronic Design, March 2001.
R.E. Bryant, K.T. Cheng, A.B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. Rabaey and A. Sangiovanni-Vincentelli, “Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI”, Proceedings of the IEEE, Special Issue on the Limits of Semiconductor Technology, pp. 341-366, March 2001.
M. Beattie, B. Krauter, L. Alatan and L. Pileggi, “Equipotential Shells for Efficient Inductance Extraction”, IEEE Transactions on Computer-Aided Design, Vol. 20, No. 1, January 2001.
E. Acar, S. Nassif and L. Pileggi, “Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations”, ACM/IEEE Workshop on Timing in the Specification and Synthesis of Digital Systems, December 2000.
M. Beattie, S. Gupta, L. Pileggi, “Hierarchical Interconnect Circuit Models”, Proceedings of the International Conference on Computer-Aided Design, November 2000.
T. Lin and L. Pileggi, “RC(L) Interconnect Sizing with Second Order Considerations”, Proceedings of the SRC Techcon Conference, September 2000.
R. Arunachalam and L.T. Pileggi, “Can We Continue to Predict Timing of ICs Prior to Manufacturing as Technologies Continue to Scale?”, ISD Magazine, September 2000.
Y. Liu, S. Nassif, L. Pileggi and A.J. Strojwas, “Impact of interconnect variations on the clock skew of a gigahertz microprocessor”, Proceedings of the Design Automation Conference, June 2000.
R. Arunachalam, K. Rajagopal and L. Pileggi, “TACO: Timing Analysis with Coupling”, Proceedings of the Design Automation Conference, June 2000.
A. Odabasioglu, M. Celik & L. T. Pileggi, “Practical Considerations for Passive Reduction of RLC Circuits”, Proceedings of the International Conference on Computer- Aided Design, November 1999.
M. Beattie and L. Pileggi, “Electromagnetic Parasitic Extraction via a Multipole Method with Hierarchical Refinement”, Proceedings of the International Conference on Computer-Aided Design, November 1999.
A. Odabasioglu, M. Celik & L. T. Pileggi, “Efficient and Accurate Delay Metrics for RC Interconnect”, PATMOS: International Workshop on Power and Timing Modeling, Optimization and Simulation, October 1999.
M. Beattie and L. Pileggi, “IC Analyses Including Extracted Inductance Models”, Proceedings of the Design Automation Conference, Invited Paper, June 1999.
Y. Liu, L. Pileggi and A.J. Strojwas, “Model Order-Reduction of RC(L) Interconnect including Variational Analysis”, Proceedings of the Design Automation Conference (Best Paper Award Nomination), June 1999.
E. Acar, A. Odabasioglu, M. Celik and L. Pileggi, “S2P: Stable 2-Pole Model for RC Interconnect Delay Analysis”, Proceedings of the 9th Great Lakes Symposium on VLSI, March 1999.
L. Pileggi, “Achieving Timing Closure for Giga-Scale IC Designs”, 1999 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Invited Paper, March 1999.
M. Beattie and L. T. Pileggi, “Bounds for BEM Capacitance Extraction”, IEEE Transactions on Computer-Aided Design, Vol. 18, No. 3, pp. 311-321, March 1999.
M. Celik and L. T. Pileggi, “Metrics and Bounds for Phase Delay and Signal Attenuation in RCL Clock Trees”, IEEE Transactions on Computer-Aided Design, Vol. 18, No. 3, pp. 293-300, March 1999.
M. Beattie, L. Alatan and L. Pileggi, “Equipotential Shells for Efficient Partial Inductance Extraction”, Proceedings of the International Electronics Devices Meeting, December 1998.
T. Lin, Emrah Acar and L. Pileggi, “h-gamma: An Interconnect Timing Metric Based on the Gamma Distribution Model for the Homogeneous Response”, Proceedings of the International Conference on Computer-Aided Design, November 1998.
P. Gross, R. Arunachalam, K. Rajagopal and L. Pileggi, “Determination of Worst-Case Aggressor Alignment for Delay Calculation”, Proceedings of the International Conference on Computer-Aided Design, November 1998.
M. Beattie and L. Pileggi, “Equipotential Shells for Efficient Inductance Extraction”, Proceedings of the SRC Techcon Conference, September 1998.
T. Lin and L. Pileggi, “Looking Beyond the Elmore Delay — Metrics for Deep Submicron”, Proceedings of the SRC Techcon Conference, September 1998.
K. Rajagopal, P. Gross and L. Pileggi, “The Impact of Coupling on Worst-Case Waveform Analysis”, Proceedings of the SRC Techcon Conference, September 1998.
F. Liu, L. Pileggi and A.J. Strojwas, “A Synthesized Driving-Point Model for Capacitively Coupled Interconnects”, Proceedings of the SRC Techcon Conference, September 1998.
Rohini Gupta, John Willis and L.T. Pileggi, “Analytic Termination Metrics for Pin-to- Pin Lossy Transmission Lines with Nonlinear Drivers”, IEEE Transactions on VLSI Systems, Vol. 6, No. 3, pp. 457-463, September 1998.
A. Odabasioglu, M. Celik and L. T. Pileggi, “PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm”, IEEE Transactions on Computer-Aided Design (1999 IEEE Best Paper Award), Vol. 17, No. 8, pp. 645-654, August 1998.
R. Kay and L. Pileggi, EWA: “Efficient Wire Sizing Algorithm”, IEEE Transactions on Computer-Aided Design, January, 1998.
Rony Kay and Lawrence Pileggi, “PRIMO: Probability Interpretation of Moments for Delay Calculation”, Proceedings of the Design Automation Conference, June 1998.
Frank Liu, Lawrence Pileggi and Andrzej Strojwas, ftd: “An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models”, Proceedings of the Design Automation Conference, June 1998.
Florin Dartu and Lawrence Pileggi, “TETA: Transistor-Level Engine for Timing Analysis”, Proceedings of the Design Automation Conference, June 1998.
Zhijiang (John) He and Lawrence T. Pileggi, “A Simple Algorithm for Calculating Frequency-Dependent Inductance Bounds”, Proceedings of the Custom Integrated Circuits Conference, May 1998.
M. Celik and L. T. Pileggi, “Simulation of Lossy Multiconductor Transmission Lines Using Backward Euler”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 45, No. 3, pp. 238-243, March 1998.
N. Menezes, R. Baldick and L.T. Pileggi, “A Sequential Quadratic Programming Approach to Concurrent Gate and Interconnect Sizing”, IEEE Transactions on Computer- Aided Design, August 1997.
G. Ellis, L.T. Pileggi, R.A. Rutenbar, “A Hierarchical Decomposition Methodology for Multistage Clock Circuits”, Proceedings of the International Conference on Computer-Aided Design, 1997.
A. Odabasioglu, M. Celik, L.T. Pileggi, “PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm”, Proceedings of the International Conference on Computer-Aided Design, 1997.
A. Mehta, Y-P. Chen, N. Menezes, L. T.Pileggi and M. Wong, “Clustering and Load Balancing for Buffered Clock Tree Synthesis”, Proceedings of the Int’l Conference on Computer Design, October 1997.
Ravishankar Arunachalam, Florentin Dartu and Lawrence T.Pileggi, “CMOS Gate Delay Models for General RLC Loading”, Proceedings of the Int’l Conference on Computer Design, October 1997.
John He, Mustafa Celik and Lawrence Pileggi, “SPIE: Sparse PEEC Inductance Extraction”, Proceedings of the Design Automation Conference, 1997.
Michael Beattie and Lawrence Pileggi, “Bounds for BEM Capacitance Extraction”, Proceedings of the Design Automation Conference, 1997.
Florin Dartu and Lawrence Pileggi, “Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling”, Proceedings of the Design Automation Conference, 1997.
R. Kay, G. Bucheuv, and L. Pileggi, “EWA: Exact Wire Sizing Algorithm”, 1997 International Symposium on Physical Design, April 1997.
G. Ellis, L. Pileggi and R. Rutenbar, “A Hierarchical Decomposition Methodology for Single-Stage Clock Circuits”, Proceedings of the Custom Integrated Circuits Conference, May 1997.
F. Liu, L. Pileggi and A.J. Strojwas, “A Sparse Macromodeling Method for RC Interconnect Multiports”, Proceedings of the Custom Integrated Circuits Conference, May 1997.
S. Pullela, N. Menezes and L.T. Pileggi, “Moment-Sensitivity-Based Wire Sizing for Skew Reduction in On-Chip Clock Nets”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 2, pp. 210-215, February 1997.
Rohini Gupta, Bogdan Tutuianu and Lawrence Pileggi, “The Elmore Delay as a Bound for RC Trees with Generalized Input Signals”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 95-104, January 1997.
Rohini Gupta, Byron Krauter and Lawrence Pileggi, “Transmission Line Synthesis via Constrained Multivariable Optimization”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 6-19, January 1997.
F. Dartu and L.T. Pileggi, “Gate-level modeling of of coupling capacitance effects”, Proceedings of the SRC Techcon Conference, October 1996.
Florin Dartu, Bogdan Tutuianu and Lawrence T. Pileggi, “RC-Interconnect Macromodels for Timing Simulation”, Proceedings of the Design Automation Conference , 1996.
Florentin Dartu and Lawrence T. Pileggi, “Modeling Signal Waveshapes for Empirical CMOS Gate Delay Models”, Sixth International Workshop on Power and Timing Modeling, Optimization and Simulation, September 1996.
Rohini Gupta and Lawrence Pileggi, “Modeling Lossy Transmission lines Using the Method of Characteristics”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 43, No. 7, pp. 580-583, July 1996.
Rohini Gupta, John Willis and Lawrence T. Pileggi, “Low Power Design of Off-Chip Drivers and Transmission lines: A Branch and Bound Approach”, International Journal of High Speed Electronics and Systems, Vol. 7, no. 9, pp. 27-45, June 1996.
S. Pullela, N. Menezes and L.T. Pileggi, “Post-Processing of Clock Trees via Wiresizing and Buffering for Robust Design”, IEEE Transactions on Computer-Aided Design, pp. 691-701, June 1996.
Byron Krauter, Yu Xia, Aykut Dengi, Lawrence T. Pileggi, “A Sparse Image Method for BEM Capacitance Extraction”, Proceedings of the Design Automation Conference, 1996.
Bogdan Tutuianu and Lawrence Pileggi, “An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response”, Proceedings of the Design Automation Conference , 1996.
F. Dartu, N. Menezes and L.T. Pileggi, “Performance Computation for Pre-characterized CMOS Gates with RC Loads”, IEEE Transactions on Computer-Aided Design, pp. 544-553, May 1996.
Rohini Gupta, Seok-Yoon Kim and Lawrence Pileggi, “Domain Characterization of Transmission Line Models and Analyses”, IEEE Transactions on Computer-Aided Design, pp. 184-193, February 1996.
R. Gupta, B. Krauter and L. Pileggi, “On Moment Based Metrics for Optimal Termination of Transmission Line Interconnects”, Proceedings of the 9th International Conference on VLSI Design, January 1996.
M. Kamon, B. Krauter, J. Phillips, L. Pileggi, and J. White, “Two Optimizations to Accelerated Method-of-Moments Algorithms for Signal Integrity Analysis of Complicated 3-D Packages”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, November 1995.
R. Gupta, B. Krauter, B. Tutuianu, J. Willis and L. Pileggi, “The Elmore Delay as a Bound for RC-Trees with Generalized Input Signals”, Proceedings of the Design Automation Conference, 1995.
N. Menezes, S. Pullela and L. Pileggi, “Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization”, Proceedings of the Design Automation Conference, 1995.
B. Krauter, R. Gupta, J. Willis and L. Pileggi, “Transmission Line Synthesis”, Proceedings of the Design Automation Conference , 1995.
I. Tesu and L. Pileggi, “Timing Analysis Models for Gates and Cells with Bipolar Transistor Output Stages”, Proceedings of the IEEE ASIC Conference, 1995.
I. Tesu and L. Pileggi, “Pre-characterization of ECL Gates for Timing Analysis”, SCS ’95 International Symposium on Signals, Circuits & Systems, Iasi, Romania, October 1995.
L. Pileggi, “Coping with RC(L) Interconnect Induced Headaches”, Proceedings of the International Conference on Computer-Aided Design, (Invited Tutorial Paper) 1995.
B. Krauter and L. Pileggi, “Generating Sparse Partial Inductance Matrices with Guaranteed Stability”, Proceedings of the International Conference on Computer-Aided Design, 1995.
N. Menezes, R. Baldick and L. Pileggi, “A Sequential Quadratic Programming Approach to Concurrent Gate and Wire Sizing”, Proceedings of the International Conference on Computer-Aided Design, 1995.
R. Gupta and L. Pileggi, “Constrained Multivariable Optimization of Transmission Lines with General Topologies”, Proceedings of the International Conference on Computer-Aided Design, 1995.
S. Pullela, N. Menezes and L.T. Pillage, “Low Power IC Clock Tree Design”, Proceedings Custom Integrated Circuits Conference, May 1995.
B. Krauter, D. Neikirk and L.T. Pillage, “Sparse Partial Inductance Matrix Formulation”, Progress in Electromagnetics Research Symposium, July 1995.
Rohini Gupta, John Willis and L.T. Pillage, “Wire Width Optimization of Transmission Lines for Low Power Design”, IEEE Multi-chip Module Conference, February 1995.
J. Qian, S. Pullela and L.T. Pillage, Modeling the “Effective Capacitance” of RC Interconnect, IEEE Transactions on Computer-Aided Design, pp. 1526-1535, December 1994.
N. Menezes, S. Pullela and L.T. Pillage, “RC Interconnect Synthesis — A Moment Fitting Approach”, Proceedings of the 1994 International Conference on Computer-Aided Design, Nov. 1994.
John Willis, Rohini Gupta and L.T. Pillage, “Metrics for RLC Transmission Line Termination”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, November 1994.
L.T. Pillage and R.A. Rohrer, “The Essence of AWE”, Circuits and Devices Magazine, November 1994.
R. Gupta, S.Y. Kim and L.T. Pillage, “Domain Characterization of Transmission Line Models for Efficient Simulation”, Proceedings of the International Conference on Computer Design, October 1994.
S.Y. Kim, N. Gopal and L.T. Pillage, “Time-Domain Macromodels for VLSI Interconnect Analysis”, IEEE Transactions on Computer-Aided Design, pp. 1257-1270, October 1994.
F. Dartu, N. Menezes, J. Qian and L.T. Pillage, “A Gate Delay Model for High Performance CMOS”, Proceedings Design Automation Conference, June 1994.
R. Gupta and L.T. Pillage, “OTTER: Optimal Termination of Transmission Lines Excluding Radiation”, Proceedings Design Automation Conference, June 1994.
D.F. Anastaskis, N. Gopal, S.Y. Kim and L.T. Pillage, “On the Stability of Moment- Matching Approximations in Asymptotic Waveform Evaluation”, IEEE Transactions on Computer-Aided Design, pp. 729-736, June 1994.
C. Ratzlaff and L.T. Pillage, “RICE: Rapid Interconnect Circuit Evaluation Using Asymptotic Waveform Evaluation”, IEEE Transactions on Computer-Aided Design, pp. 763-776, June 1994.
N. Gopal, A. Balivada and L.T. Pillage, “Moment-Matching Approximations for Linear(ized) Circuit Analysis, Semiconductors in IMA Volumes in Mathematics and it’s Applications”, F. Odeh, J. Cole, W. M. Coughran, Jr., P. Lloyd, and J. White, editors, Springer-Verlag, pp. 115-130, May 1994.
R.B. Brashear, N. Menezes, C. Oh, L.T. Pillage and M.R. Mercer, “Predicting Circuit Performance Using Circuit-Level Statistical Timing Analysis”, Proceedings of the European Design Automation Conference, February 1994.
S. Pullela, N. Menezes and L.T. Pillage, “Skew and Delay Optimization for Reliable Buffered Clock Trees”, Proceedings of the 1993 International Conference on Computer-Aided Design, Nov. 1993.
S. Y. Kim, E. Tuncer, R. Gupta, B. Krauter, T.L. Savarino, D. P. Neikirk and L. T. Pillage, “An Efficient Methodology for Extraction and Simulation of Transmission Lines for Application Specific Electronic Modules”, Proceedings of the 1993 International Conference on Computer-Aided Design, Nov. 1993.
E. Tuncer, S.Y. Kim, L.T. Pillage and D. Neikirk, A New, “Efficient Circuit Model for Microstrip Lines Including Both Current Crowding and Skin Depth Effects”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, October 1993.
S. Pullela, N. Menezes and L.T. Pillage, “Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization”, Proceedings Design Automation Conference, June 1993.
D.C. Yuan, L.T. Pillage, and J.T. Rahmeh, “Evaluation by Parts of Mixed-Level dc- Connected Components in Logic Simulation”, Proceedings Design Automation Conference, June 1993.
S.Y. Kim, N. Gopal and L.T. Pillage, “Finite-Pole Macromodels of Transmission Lines for Circuit Simulation”, Proceedings Custom Integrated Circuits Conference, May 1993.
V. Raghavan, R.A. Rohrer, L.T. Pillage, J.Y. Lee, J.E. Braken, M.M. Alaybeyi, AWE-Inspired, “Proceedings Custom Integrated Circuits Conference”, (Invited Tutorial Paper), May 1993.
N. Menezes, S. Pullela, A. Balivada and L.T. Pillage, “Skew Reduction in Clock Trees Using Wire Width Optimization”, Proceedings Custom Integrated Circuits Conference, May 1993.
S.Y. Kim, N. Gopal and L.T. Pillage, “AWE Macromodels for Incorporation in a Circuit Simulator”, Proceedings IEEE International Conference on Computer-Aided Design, November 1992.
R. Brashear, D. Holberg, M.R. Mercer and L.T. Pillage, “ETA: Electrical-Level Timing Analysis”, Proceedings IEEE International Conference on Computer-Aided Design, November 1992.
D. F. Anastasakis, N. Gopal, S.Y. Kim and L.T. Pillage, “On the Stability of Moment Matching Approximations in Asymptotic Waveform Evaluation”, Proceedings Design Automation Conference, June 1992.
N. Gopal, E. Tuncer, D. Neikirk and L.T. Pillage, “Non-Uniform Models for Transmission Line Analysis”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, April, 1992.
C. Ratzlaff, S. Pullela and L.T. Pillage, “Effects of RC-Interconnect in a Hierarchical Timing Analyzer”, Proceedings Custom Integrated Circuits Conference, May 1992.
N. Gopal, D. Neikirk and L.T. Pillage, “Evaluating RC Interconnect Using Moment Methods” Proceedings IEEE International Conference on Computer-Aided Design, November 1991.
N. Gopal, C. Ratzlaff, L.T. Pillage, “Constrained Approximation of Dominant Time Constants in RC Circuit Delay Models”, Proceedings of the International Mathematics and Computation Symposium, (Invited Paper), July 1991.
C. Ratzlaff, N. Gopal, L.T. Pillage, “RICE: Rapid Interconnect Circuit Evaluator”, Proceedings Design Automation Conference, (Best Paper Award Nomination), June 1991.
A. Balivada, D. Holberg and L.T. Pillage, “Calculation and Application of Time-Domain Sensitivities in Asymptotic Waveform Evaluation”, Proceedings Custom Integrated Circuits Conference, May 1991.
D. Holberg, S. Dutta and L.T. Pillage, “DC Parametrized Piecewise Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation”, Proceedings IEEE International Conference on Computer-Aided Design, November 1990.
S. Dutta and L.T. Pillage, “Calculating the Moments in AWE With Linear Complexity”, Proceedings of the SRC Techcon Conference, October 1990.
L.T. Pillage and S. Dutta, “A Path Tracing Algorithm for Asymptotic Waveform Evaluation of RLC Circuit Delay Models”, 1990 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, August 1990.
L.T. Pillage, X. Huang and R.A. Rohrer, “Asymptotic Waveform Evaluation for Circuits Containing Floating Nodes”, Proceedings IEEE International Symposium on Circuits and Systems, May 1990.
L.T. Pillage and R.A. Rohrer, “Asymptotic Waveform Evaluation”, IEEE Transactions on Computer-Aided Design (1991 IEEE Best Paper Award), pp. 352-366, April 1990.
L.T. Pillage, X. Huang and R.A. Rohrer, “AWEsim: Asymptotic Waveform Evaluation for Timing Analysis”, Proceedings Design Automation Conference, June 1989.
L.T. Pillage, X. Zhang and R.A. Rohrer, “Efficient Final Placement Based on Nets-as- Points”, Proceedings Design Automation Conference, June 1989.
L.T. Pillage, C. Wolff and R.A. Rohrer, “Frequency Response Simulation”, Proceedings Custom Integrated Circuits Conference, May 1989.
L.T. Pillage and R.A. Rohrer, “Delay Evaluation with Lumped Linear RLC Interconnect Circuit Models”, Proceedings Decennial Caltech Conference on VLSI, March 1989.
L.T. Pillage and R.A. Rohrer, “A Quadratic Metric for the Initial Placement Problem with a Simple Solution Scheme”, Proceedings Design Automation Conference, June 1988.
L.T. Pillage, X. Huang and R.A. Rohrer, “TALISMAN: A Piecewise Linear Circuit Simulator Based on Tree Link Analysis”, Proceedings IEEE International Conference on Computer-Aided Design, November 1987.
L.T. Pillage, X. Huang and R.A. Rohrer, “Tree Link Partitioning for the Implicit Solution of Circuits”, Proceedings IEEE International Symposium on Circuits and Systems, May 1987.
| 2019 | 2018 | 2017 | 2016 | 2015 | 2014 | 2013 | 2012 | 2011 | 2010 | 2009 | 2008 | 2007 | 2006 | 2005 | 2004 | 2003 | 2002 | 2001 | 2000 | 1999 | 1998 | 1997 | 1996 | 1995 | 1994 | 1993 | 1992 | 1991 | 1990 | 1989 | 1988 | 1987 |
2019
F. Sadi , Joe Sweeney, T. M. Low, J. C. Hoe, L. Pileggi, F. Franchetti, “Efficient SpMV operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization,” IEEE/ACM International Symposium on Microarchitecture, October 2019.
S. Pagliarini, S. Bhuin, M. Isgenc, A. Biswas, L. Pileggi, A Probabilistic Synapse with Strained MTJs for Spiking Neural Networks, IEEE Transactions on Neural Networks and Learning Systems, June 2019.
A. Jovicic, M. Jereminov, L. Pileggi, G. Hug, “A Linear Formulation for Power System State Estimation including RTU and PMU Measurements,” IEEE PES Innovative Smart Grid Technologies Europe Conference, 2019.
A. Pandey, A. Agarwal, M. Jereminov, M.R. Wagner, D.M. Bromberg, L. Pileggi, “Robust Sequential Steady-State Analysis of Cascading Outages,” IEEE PES Innovative Smart Grid Technologies Europe Conference, 2019.
A. Agarwal, A. Pandey, M. Jereminov, L. Pileggi, “Implicitly Modeling Frequency Control with Power Flow,” IEEE PES Innovative Smart Grid Technologies Europe Conference, 2019.
A. Pandey, A. Agarwal, M. Jereminov, B. Rawn, T. Nwachuku and L. Pileggi, “Improving Voltage Profile of the Nigerian Power Grid,” in Proc. IEEE PES/IAS PowerAfrica Conference, Abuja Nigeria, August 2019.
M. Jereminov, A. Terzakis, M. Wagner, A. Pandey, L. Pileggi, “Robust and Efficient Power Flow Convergence with G-min Stepping Homotopy Method,” in Proc. IEEE Conference on Environment, Electrical Engineering and I&CPS Europe, Genoa, Italy, June 2019.
M. R. Wagner, M. Jereminov, A. Pandey, and L. Pileggi, “A Probabilistic Approach to Power System State Estimation using a Linear Algorithm,” in 2019 IEEE Conference on Environment and Electrical Engineering and I&CPS Europe, 2019.
M. Jereminov, A. Jovicic, M. Wagner, G. Hug, L. Pileggi, “Equivalent Circuit Programming for Estimating the State of a Power System,” in Proc. IEEE PowerTech Milan, June 2019.
M. R. Wagner, M. Jereminov, A. Pandey, and L. Pileggi, “A Probabilistic Approach to Power System State Estimation using a Linear Algorithm,” in 2019 IEEE Conference on Environment and Electrical Engineering and I&CPS Europe, 2019.
2018
M. Jereminov, A. Pandey, L. Pileggi, Equivalent Circuit Formulation for Solving AC Optimal Power Flow, IEEE Transactions on Power Systems, December 2018.
S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, December 2018.
S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “Application and Product-Volume Specific Customization of BEOL Metal Pitch,” IEEE Transactions on VLSI, Vol. 26, Issue:9, pp. 1627-1636, September 2018.
B. Hooi, D. Eswaran, A. Pandey, M. Jereminov, L. Pileggi, and C. Faloutsos, “ChangeDAR: Online Localized Change Detection for Sensor Data on a Graph,” (Best Student Paper Award, Runner Up), Proceedings of the 2018 ACM Conference on Information and Knowledge Management, 2018.
T. Jackson, S. Pagliarini and L. Pileggi, “An Oscillatory Neural Network with Programmable Resistive Synapses,” in 28 nm CMOS, IEEE International Conference on Rebooting Computing, November 2018.
A. Jovicic, M. Jeremino, L. Pileggi and G. Hug, “An Equivalent Circuit Formulation for Power System State Estimation including PMUs,” (Best Paper Award, Second Prize), 50th North American Power Symposium, October 2018.
B. Hooi, D. Eswaran, H.A. Song, A. Pandey, M. Jereminov, L. Pileggi, and C. Faloutsos. “GridWatch: Sensor Placement and Anomaly Detection in the Electrical Grid,” European Conference on Machine Learning and Principles and Practice of Knowledge Discovery in Databases (ECML-PKDD) 2018.
S. Liu, T. Rabuske, L. Pileggi, J. Fernandez, J. Paramesh, “A 125 Ms/S 10.4 ENOB 10.1 fJ/conv-Step Multi-Comparator SAR ADC with Comparator Noise Scaling in 65nm CMOS,” IEEE European Solid-State Circuits conference, September 2018.
M.R. Wagner, A. Pandey, M. Jereminov, and L. Pileggi. Robust Probabilistic Analysis of Transmission Power Systems based on Equivalent Circuit Formulation, Proceedings of the International Conference on Probabilistic Methods Applied to Power Systems, June 2018.
Sadi, F., Sweeney, J., McMillan, S., Low, T. M., Hoe, J., Pileggi, L., & Franchetti, F., “PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV”. HPEC: High Performance Embedded Computing Annual Workshop(2018).
2017
H.A. Song, B. Hooi, A. Pandey, M. Jereminov, L. Pileggi, C. Faloutsos, “PowerCast: Mining and Forecasting Power Grid Sequences”, ECML-PKDD 2017 Conference, September 2017.
E. Calayir, J. Xu, L. Pileggi, G. K. Fedder, N. Singh, S. Merugu and G. Piazza, “Self-healing Narrowband Filters via 3D Heterogeneous Integration of AlN MEMS and CMOS chips”, 2017 IEEE International Ultrasonics Symposium (IUS), Washington, D.C., September 2017.
S. Bhuin, J. Sweeney, S. Pagliarini, A. K. Biswas, L. Pileggi, “A Self-Calibrating Sense Amplifier for A True Random Number Generator Using Hybrid FinFET-Straintronic MTJ”, IEEE International Symposium on Nanoscale Architectures (NANOARCH), July 2017.
T. C. Jackson and L. Pileggi, “A Mixed-Signal Oscillatory Neural Network Architecture for Integration with Resistive Crossbar Memory Arrays”, TECHCON 2017, Austin, Texas.
S. Bhuin and L. Pileggi, “A Self-Calibrating Sense Amplifier for a True Random Number Generator Using Strained MTJ”, TECHCON 2017, Austin, Texas.
M. Jereminov, A. Pandey, H.A. Song, B. Hooi, C. Faloutsos, L. Pileggi, “Linear Load Model for Robust Power System Analysis”, IEEE PES Integrative Smart Grid Technologies Europe, September 2017.
S. Bhuin, A. Biswas, L.Pileggi, “Strained MTJs with Latch-based Sensing for Stochastic Computing”, IEEE International Conference on Nanotechnology, July 2017.
J. Xu, G. Piazza, L. Pileggi and G. K. Fedder, “Reconfigurable AlN resonator filter design based on extended statistical element selection” 2017 Transducers – 2017 19th International Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS),Kaohsiung, June 2017.
A. Pandey, M. Jereminov, G. Hug, and L. Pileggi, “Improving Power Flow Robustness via Circuit Simulation Methods”, IEEE PES General Meeting, (Prize Paper Award), July 2017.
S. Pagliarini, M. Martins, L. Pileggi, “Virtual Characterization for Exhaustive DFM Evaluation of Logic Cell Libraries”, 18th International Symposium on Quality Electronic Design (ISQED), March 2017.
2016
A. Pandey, M. Jereminov, X. Li, G. Hug, L. Pileggi, “Aggregated Load and Generation Equivalent Circuit Models with Semi-Empirical Data Fitting”, IEEE Green Energy and Systems Conference (IGESC 2016), November 2016.
M. Isgenc, M. Martins, S. Pagliarini, L. Pileggi, “Exhaustive DFM evaluation of logic cell libraries via virtual characterization, IEEE/ACM Workshop on Variability Modeling and Characterization”, November 2016.
M. Jereminov, A. Pandey, G. Hug, X. Li and L. Pileggi, “Steady-State Analysis of Power System Harmonics Using Equivalent Split-Circuit Models”, IEEE PES Integrative Smart Grid Technologies Europe, October 2016.
A. Pandey, M. Jereminov, G. Hug, X. Li and L. Pileggi, “Unified Power System Analyses and Models using Equivalent Circuit Formulation”, IEEE PES Innovative Smart Grid Technologies Conference, September 2016.
R. Carley, G. Colak, L. Chomas, L. Pileggi and K. Mai, “Technologies for Secure RFID Authentication of Medicinal Pills and Capsules”, IEEE International Conference on RFID Technology and Applications (RFID-TA), September 2016.
R. Shi, T. Jackson, B. Swenson, S. Kar and L. Pileggi, “On the Design of Phase Locked Loop Oscillatory Neural Networks: Mitigation of Transmission Delay Effects”, International Joint Conference on Neural Networks, July 2016.
R. Liu, J. Weldon and L. Pileggi, “Extended Statistical Element Selection: A Calibration Method for High Resolution in Analog/RF Designs”, Design Automation Conference (DAC 2016), June 2016.
M. Jereminov, D. Bromberg, X. Li, G. Hug and L. Pileggi, “Improving Robustness and Modeling Generality for Power Flow Analysis” IEEE PES Transmission and Distribution Conference, Dallas, Texas, May 2016.
M. Jereminov, D. Bromberg, A. Pandey, G. Hug, X. Li and L. Pileggi, “An Equivalent Circuit Formulation for Three-Phase Power Flow Analysis of Distribution Systems” IEEE PES Transmission and Distribution Conference, Dallas, Texas, May 2016.
M. Darwish, V. Calayir, L. Pileggi, J. Weldon, “Ultra-Compact Graphene Multigate Variable Resistor for Neuromorphic Computing”, IEEE Transactions on Nanotechnology, Vol. 15, No. 2, March 2016.
2015
R. Liu and L. Pileggi, “Low-Overhead Self-Healing Methodology for Current Matching in Current-Steering DAC”, IEEE Transactions on Circuits and Systems II, vol 62, no. 7, pp. 651-655, July 2015.
K. Vaidyanathan, Q. Zhu, L. Liebmann, K. Lai, S. Wu, R. Liu, Y. Liu, A.J. Strojwas, and L. Pileggi, “Exploiting Sub-20 nm CMOS Technology Challenges to Design Affordable SoCs”, Journal of Micro/Nanolithography, J. Micro/Nanolith. MEMS MOEMS, 14(1), 011007, July 2015.
R. Liu, L. Pileggi and J. A. Weldon, “A Wideband RF Receiver with Extended Statistical Element Selection Based Harmonic Rejection Calibration”, Integration the VLSI Journal, June 2015.
T. C. Jackson, A. A. Sharma, J. A. Bain, J. A. Weldon, L. Pileggi, “Oscillatory Neural Networks based on TMO Nano-Oscillators and Multi-Level RRAM Cells”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), June 2015.
V. Calayir and L. Pileggi, “Device Requirements and Technology-driven Architecture Optimization for Analog Neurocomputing”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 5, no. 2, pp. 162-173, June 2015.
X. Chen, D. Bromberg, G. Hug, X. Li and L. Pileggi, ” A Robust and Efficient Power Series Method for Tracing PV Curves”, The 47th North American Power Symposium, October 2015.
T. C. Jackson, A. A. Sharma, R. Shi, J. Weldon, and L. Pileggi, “Using TMO-based RRAM Multi-Level Cells and Nano-Oscillators for Efficient ONN Implementation”,TECHCON 2015, Austin, Texas.
A. Sharma, T. Jackson, J. Bain, L. Pileggi and J. Weldon, “High Performance, Integrated 1T1R Oxide-based Oscillator: Stack Engineering for Low-Power Operation in Neural Network Applications”,in IEEE Symp. VLSI Technology, June 2015.
H.E. Sumbul, K. Vaidyanathan, Q. Zhu, F. Franchetti, L. Pileggi, “Application-Specific Synthesis of Embedded Logic-in-Memory Designs”, manuscript accepted for publishing in Design Automation Conference (DAC 2015), June 2015.
E. Calayir, J. Xu, A. Patterson, G. K. Fedder, G. Piazza, L. Pileggi, “3D Integration of AlN MEMS Filters and CMOS for Self-Healing RF Front-Ends”,Government Microcircuit Applications and Critical Technology Conference, March 2015.
2014
V. H-C. Chen and L. Pileggi, “A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI”, Special Issue of the IEEE Journal on Solid State Circuits (Invited Paper), vol.49, no.12, pp.2891,2901, Dec. 2014.
S. Sun, F. Wang, S. Yaldiz, X. Li, L. Pileggi, A. Natarajan, M. Ferriss, J.-O. Plouchart, B. Sadhu, B. Parker, A. Valdes Garcia, M.A.T. Sanduleanu, J. Tierno, and D. Friedman, “Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits”, IEEE Transactions on Circuits and Systems, vol.61, no.8, pp.2243,2252, Aug. 2014.
K. Vaidyanathan, R. Liu, L. Liebmann, K. Lai, A. Strojwas, L. Pileggi, “Design Implications of Extremely Restricted Patterning”, Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol 13 (03), 2014.
M. Jun, R. Negi, Y.-C. Wang, T. Mukherjee, X. Li, J. Tao, and L. Pileggi, “Joint Invariant Estimation of RF impairments for Reconfigurable Radio Frequency(RF) Front-end”, Globecom Workshop – Emerging Technologies for 5G Wireless Cellular Networks, 2014.
D. Bromberg, M. Moneck, V. Sokalski, L. Pileggi, J-G. Zhu, “Experimental Demonstration of Four-Terminal Magnetic Logic Device with Separate Read- and Write-Paths, International Electron Devices Meeting”, December 2014.
D.M. Bromberg, E. Sumbul, J-G. Zhu and L. Pileggi, “All-Magnetic MRAM Based on Four Terminal mCell Device”, 13th Joint MMM/Intermag Conference, November 2014.
Minhee Jun, Jun Tao, Ying-Chih Wang, Shihui Yin, Rohit Negi, Xin Li, Tamal Mukherjee and Lawrence Pileggi, “Environment-adaptable efficient optimization for programming of reconfigurable radio frequency (RF) receivers”, IEEE Military Communications Conference (MILCOM), 2014.
F. Sadi, B. Akin, D. Popovici, J. Hoe, L. Pileggi, F. Franchetti, “Algorithm/Hardware Co-optimized SAR Image Reconstruction with 3D-stacked Logic in Memory”, Eighteenth Annual High Performance Embedded Computing (HPEC) Workshop at MIT Lincoln Laboratory, September 2014.
R. Liu, L. Pileggi and J. Weldon, “A Wideband RF Receiver with >80 dB Harmonic Rejection Ratio”, Int’l Custom Integrated Circuits Conference, September 2014.
K. Vaidyanathan, L. Liebmann, A. Strojwas, L. Pileggi, “Sub-20 nm Design Technology Co-Optimization for Standard Cell Logic”, Int’l Conference on Computer-Aided Design, November 2014.
2013
C.Y. Wen, G. Slovin, J. Bain, E. Schlesinger, L. Pileggi and J. Paramesh, “A Phase-Change Via-Reconfigurable CMOS LC VCO”, IEEE Transactions on Electron Devices, Vol. 60, No. 12, pp 3979-3988, December 2013.
D.H. Morris, D.M. Bromberg, J-G. ZHU and L. Pileggi, “Spintronic Devices and Circuits for Low-Voltage Logic”, International Journal of High Speed Electronics and Systems Vol. 21, No. 1 (2012) 1250005.
Qiuling Zhu, Berkin Akin, H. Ekin Sumbul, James C. Hoe, Larry Pileggi, Franz Franchetti, “A 3D-Stacked Logic-in-Memory Accelerator for Application-Specific Data Intensive Computing”, IEEE International 3D Systems Integration Conference, October 2013.
S. Sun, F. Wang, S. Yaldiz, X. Li, L. Pileggi, A. Natarajan, M. Ferriss, J. Plouchart, B. Sadhu, B. Parker, A. Valdes-Garcia, M. Sanduleanu, J. Tierno, D. Friedman, “Indirect Performance Sensing for On-Chip Analog Self-Healing via Bayesian Model Fusion”, Int’l Custom Integrated Circuits Conference, September 2013.
Qiuling Zhu, Tobias Graf, H. Ekin Sumbul, Larry Pileggi, Franz Franchetti, “A Logic-in-Memory Accelerated 3D-DRAM for Sparse Matrix-Matrix Multiplication”, Seventeenth Annual High Performance Embedded Computing (HPEC) Workshop at MIT Lincoln Laboratory (Best Paper Award), September 2013.
V. Calayir, T. Jackson, A. Tazzoli, G. Piazza and L. Pileggi, “Neurocomputing and Associative Memories Based on Ovenized Aluminum Nitride Resonators”, International Joint Conference on Neural Networks, August 2013.
V. Calayir and L. Pileggi, “All-Magnetic Analog Associative Memory”, International NEWCAS Conference, June 2013.
V. Calayir and L. Pileggi, “Fully-Digital Oscillatory Associative Memories Enabled by Non-volatile Logic”, International Joint Conference on Neural Networks, August 2013.
V. H.-C. Chen and L. Pileggi, “An 8.5mW 5GS/s 6b Flash ADC with Dynamic Offset Calibration in 32nm CMOS SOI”, in IEEE Symp. VLSI Circuits, June 2013.
B. Sadhu, M.A. Ferriss, A.S. Natarajan, S. Yaldiz, J-O. Plouchart, A.V. Rylyakov, A. Valdes-Garcia, B.D. Parker, A. Babakhani, S. Reynolds, X. Li, L. Pileggi, R. Harjani, J. Tierno and D. Friedman, “A Linearized Low Noise VCO-Based PLL With Automatic Biasing”, IEEE Journal of Solid State Circuits (Invited), Volume 48 , Issue 5, May 2013.
2012
Q. Zhu, C. Berger, E. Turner, L. Pileggi and F. Franchetti, “Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation”, Journal of Signal Processing Systems, 2012.
Q. Zhu, L. Pileggi and F. Franchetti, Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography, Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October 2012.
J.-O. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakani, S. Yaldiz, L. Pileggi, R. Harjani, S. Reynolds, J. A. Tierno, D. Friedman, “A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS”, Int’l Custom Integrated Circuits Conference, Sept. 2012.
Q. Zhu, L. Pileggi and F. Franchetti, “Smart Memory Synthesis for Energy-Efficient Computed Tomography Reconstruction”, Proceedings of the SRC Techcon Conference, September 2012.
Q. Zhu, K. Vaidyanathan, O. Shacham, M. Horowitz, L. Pileggi and F. Franchetti, “Design Automation Framework for Application-Specific Logic-in-Memory Blocks”, IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2012.
B. Sadhu, M.A. Ferriss, J-O. Plouchart, A.S. Natarajan, A.V. Rylyakov, A. Valdes-Garcia, B.D. Parker, S. Reynolds, A. Babakhani, S. Yaldiz, L. Pileggi, R. Harjani, J. Tierno and D. Friedman, “A 21.8-27.5GHz PLL in 32nm SOI Using Gm Linearization to Achieve -130dBc/Hz Phase Noise at 10MHz Offset from a 22GHz Carrier”, 2012 Radio Frequency Integrated Circuits Symposium, June 2012.
D. Morris, D. Bromberg, J. Zhu and L. Pileggi, “Magnetic Logic Circuits with Minimal Connections to CMOS”, IEEE CAS-FEST, 2012.
D. Morris, D. Bromberg, J. Zhu and L. Pileggi, “mLogic: Ultra-Low Voltage Non-Volatile Logic Circuits Using STT-MTJ Devices”, IEEE/ACM Design Automation Conference (DAC), 2012.
D. Morris, D. Bromberg, J. Zhu, and L. Pileggi, “Spintronic Circuits and Devices for Low-Voltage Electronics”, (Invited Paper) In Proceedings of WOFE, 2011.
Q. Zhu, L. Pileggi , F. Franchetti, “Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography”, VLSI-SoC, October 2012.
2011
D. Morris, D. Bromberg, J. Zhu, and L. Pileggi, “mLogic: Ultra-Low Voltage Logic Circuits with Non-Volatile Spintronic Devices”, (Invited Paper) Workshop on Frontier Electronics, December 2011.
J. Zhu, D. Bromberg, D. Morris and L. Pileggi, “Novel STT Device Design To Enable All Metallic Spin Logic Circuits Free of Transistors”, (Invited Presentation) Conference on Magnetism and Magnetic Materials, October 2011.
M. Althoff, A. Rajhans, B. Krogh, S. Yaldiz, X. Li and L. Pileggi, “Formal Verification of Phase-Locked Loops Using Reachability Analysis and Continuization”, Int’l Conference on Computer-Aided Design (Best Paper Award), November 2011.
Qiuling Zhu, Franz Franchetti and Larry Pileggi, “Application-Specific Logic-in-Memory for Polar Format Synthetic Aperture Radar”, Fifteenth Annual High Performance Embedded Computing (HPEC) Workshop at MIT Lincoln Laboratory, September 2011.
S. Yaldiz, V. Calayir, X. Li, L. Pileggi, et al, “Indirect Phase Noise Sensing for Self-Healing Voltage Controlled Oscillators”, Int’l Custom Integrated Circuits Conference, Sept. 2011.
C.-Y. Wen, J. Paramesh, L. T. Pileggi, J. Li, S. Kim, J. Proesel, C. Lam, “Post-Silicon Calibration of Analog CMOS Using Phase-Change Memory Cells”, European Solid-State Device Research Conference (ESSDERC), September 2011.
M. Althoff, A. Rajhans, B.H. Krogh, S. Yaldiz, X. Li, L. Pileggi, “Using Continuization in Reachability Analysis for the Verification of a Phase-Locked Loop”, In Proc. Frontiers in Analog Circuit (FAC) Synthesis and Verification, July 2011.
D. Morris, K. Vaidyanathan and L. Pileggi, “Design Without Rules: A Pattern Construct Methodology”, Proceedings of the SRC Techcon Conference, September 2011.
D. Morris, K. Vaidyanathan, N. Lafferty, K. Lai, L. Liebmann, L. Pileggi, “Design of Embedded Memory and Logic Based On Pattern Constructs”, IEEE Symposium on VLSI (Invited Presentation), June 2011.
C.-Y. Wen, J. Li, S. Kim, M. Breitwisch, C. Lam, J. Paramesh, L. T. Pileggi, “A Non-volatile Look-Up Table Design Using PCM (Phase-Change Memory) Cells”, IEEE Symposium on VLSI, June 2011.
2010
C.-Y. Wen, E. K. Chua, R. Zhao, T. C. Chong, J. A. Bain, T. E. Schlesinger, L. T. Pileggi, J. Paramesh, “A Phase-change via-Reconfigurable On-Chip Inductor”, International Electron Devices Meeting, December 2010.
G. Keskin, J. Proesel and L. Pileggi, “Statistical Modeling and Post Manufacturing Configuration for Scaled Analog CMOS”, Int’l Custom Integrated Circuits Conference, Sept. 2010.
J. Proesel, G. Keskin, J.O. Plouchart and L. Pileggi, “An 8-bit 1.5GS/s Flash ADC Using Post-Manufacturing Statistical Selection”, Int’l Custom Integrated Circuits Conference, Sept. 2010.
A. Bonnoit, S. Herbert and L. Pileggi, “Reducing Variability in Chip-Multiprocessors with Adaptive Body Biasing”, International Symposium on Low Power Electronics and Design, August 2010.
G. Keskin, J. Proesel and L. Pileggi, “Modeling of Statistical Element Selection Based Self-Healing Analog Circuits”, Proceedings of the SRC Techcon Conference, September 2010.
D. Morris, S. Rovner, L. Pileggi, A. Strojwas and K. Vaidyanathan, “Enabling Application-Specific Integrated Circuits on Limited Pattern Constructs”, IEEE Symposium on VLSI (Invited Presentation), June 2010.
Tejas Jhaveri, Vyacheslav Rovner, Lars Liebmann, Larry Pileggi, Andrzej Strojwas, Jason D. Hibbeler, “Design Technology Co-optimization for Predictive Technology Scaling Beyond Gratings, Invited Keynote Paper”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 4, April 2010.
L. Liebmann, J. Hibbeler, N. Hieter, L. Pileggi, M. Moe, T. Jhaveri, V. Rovner, “Demonstrating the benefits of template-based design-technology co-optimization”, SPIE Advanced Lithography Conference, February 2010.
T. Jhaveri, U. Urslan, V. Rovner, L. Pileggi & A. J. Strojwas, “Application of the Cost-Per-Good-Die Metric for Process-Design Co-optimization”, SPIE Advanced Lithography Conference, Selected for Keynote Presentation, February 2010.
2009
A. Bonnoit, S. Herbert, L. Pileggi and D. Marculescu, “Integrating Dynamic Voltage/Frequency Scaling and Adaptive Body Biasing using Test-time Voltage Selection”, International Symposium on Low Power Electronics and Design, August 2009.
J. Proesel, G. Keskin and L. Pileggi, “An 8-bit Flash ADC using Statistical Element Selection”, Proceedings of the SRC Techcon Conference, September 2009.
U. Arslan, J. Wang and L. Pileggi, “An SRAM Design Framework for Deeply-Scaled CMOS”, Proceedings of the SRC Techcon Conference, September 2009.
B. Taylor, D. Morris and L. Pileggi, “Fixed Depth Reasoning in Satisfiability and its Applications to Combinatorial Optimization”, Proceedings of the SRC Techcon Conference, September 2009.
T. Jhaveri, A. J. Strojwas, L. Pileggi and V. Rovner, “Economic Assessment of Lithography Strategies for the 22nm Technology Node”, Proceedings of the SPIE/BACUS Symposium on Photomask Technology, September 2009.
A. J. Strojwas, T. Jhaveri, V. Rovner and L. Pileggi, “Creating an Affordable 22nm Node using Design-Lithography Co-Optimization”, Proceedings of ACM/IEEE Design Automation Conference, June 2009.
J. Wang, S. Yaldiz, X. Li and L. Pileggi, “SRAM Parametric Failure Analysis, Proceedings of ACM/IEEE Design Automation Conference”, June 2009.
S. Yaldiz, U. Arslan, X. Li and L. Pileggi, “Efficient Statistical Analysis of Read Timing Failures in SRAM Circuits”, IEEE Int’l Symposium on Quality in Electronic Design, March 2009.
Lars Liebmann, Larry Pileggi, Jason Hibbeler, Vyacheslav Rovner, Tejas Jhaveri, Greg Northrop, “Simplify to Survive: Prescriptive Layouts Ensure Profitable Scaling to 32nm and Beyond”, SPIE Advanced Lithography Conference, February 2009.
Tejas Jhaveri, Andrzej Strojwas, Larry Pileggi & Vyacheslav Rovner, “OPC Simplification & Mask Cost Reduction using Regular Design Fabrics”, SPIE Advanced Lithography Conference, February 2009.
2008
Bin Wan, Jian Wang, Gokce Keskin, and Lawrence T. Pileggi, “Ring Oscillators for Single Process-Parameter Monitoring”, IEEE Workshop on Test Structure Design for Variability Characterization, November 2008.
J. Proesel and L. Pileggi, ‘A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS’, Int’l Custom Integrated Circuits Conference, Sept. 2008.
U. Arslan, M. McCartney, M. Bhargava, X. Li, K. Mai and L. Pileggi, “Variation-Tolerant SRAM Sense-Amplifier Timing Using Configurable Replica Bitlines”, Int’l Custom Integrated Circuits Conference, Sept. 2008.
L. Pileggi, G. Keskin, X. Li, K. Mai and J. Proesel, “Mismatch Analysis and Statistical Design at 65 nm and Below”, Invited Paper, Int’l Custom Integrated Circuits Conference, Sept. 2008.
U. Arslan, M. McCartney, M. Bhargava, L. Pileggi and K. Mai, “Variation-Tolerant SRAM Sense-Amp Timing using Configurable Replica Bitlines”, Proceedings of the SRC Techcon Conference, September 2008.
J. Proesel and L. Pileggi, “A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS”, Proceedings of the SRC Techcon Conference, September 2008.
G. Keskin, L. Pileggi, X. Li and K. Mai, “Process Variation Effects on Input Offset Voltage of CMOS SRAM Sense Amplifiers”, Proceedings of the SRC Techcon Conference, September 2008.
Xin Li, Jiayong Le, Mustafa Celik and Lawrence Pileggi, “Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 6, pp. 1041-1054, June 2008.
E. Small, S.M. Sadeghipour, L. Pileggi, M. Asheghi, “Thermal Analyses of Confined Cell Design for Phase Change Random Access Memory (PCRAM)”, ITherm, May 2008.
Xin Li, Yaping Zhan and Lawrence Pileggi, “Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 5, pp. 831-843, May 2008.
2007
B. Taylor and L. Pileggi, “Exact Methods for Physical Design of Regular Logic Bricks”, Proceedings of the SRC Techcon Conference, October 2007.
X. Li, B. Taylor, Y-T. Chen and L. Pileggi, “Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization” , Proceedings of the International Conference on Computer-Aided Design, November 2007.
K. Yu, S. Wang, A. Gerdemann, C. Weldon, D. Reber, J. Vasek, S. Veeraraghavan, V. Rovner, T. Jhaveri, T. Hersan, L. Pileggi”,Regular Layout Performance Dependence on Cell Abutment”, Joint Conference on Design For Manufacturing, June 2007.
J. Wang, X. Li and L. Pileggi, “Parameterized Macromodeling for Analog System-Level Design Exploration”, Proceedings of ACM/IEEE Design Automation Conference, June 2007.
B.Taylor and L. Pileggi, “Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks”, Proceedings of ACM/IEEE Design Automation Conference, June 2007.
X. Li and L. Pileggi, “Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits”, Proceedings of ACM/IEEE Design Automation Conference, June 2007.
Xin Li, Jiayong Le, Lawrence Pileggi, “Statistical Performance Modeling and Optimization”, Foundations and Trends in Electronic Design Automation: Vol. 1: No 4, pp 331-480, January 2007.
Tejas Jhaveri, Vyacheslav Rovner, Larry Pileggi, Andrzej J. Strojwas, et al., “Maximization of Layout Printability/Manufacturability by Extreme Layout Regularity”, Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol 6 (03), January 2007.
Xin Li, Jiayong Le, Padmini Gopalakrishnan and Lawrence Pileggi, “Asymptotic probability extraction for non-Normal performance distributions”, IEEE Trans. on Computer-Aided Design of Integrated Circuits (TCAD), January 2007.
Xin Li, Padmini Gopalakrishnan, Yang Xu and Lawrence Pilegg, “Robust analog/RF circuit design with projection-based performance modeling”, IEEE Trans. on Computer-Aided Design of Integrated Circuits (TCAD), January 2007.
2006
K.Y. Tong, V. Rovner, L. Pileggi and V. Kheterpal, “Design Methodology of Regular Logic Bricks for Robust Integrated Circuits”, Int’l Conference on Computer Design, October 2006.
G. Keskin, X. Li and L. Pileggi, “Active On-Die Suppression of Power Supply Noise”, Int’l Custom Integrated Circuits Conference, Sept. 2006.
P. Li, L. Pileggi, M. Ashegi, R. Chandra, “Efficient Full-Chip Thermal Modeling and Analysis”, IEEE Transactions on CAD, Vol. 25, Issue 9, pp. 1763 – 1776, Sept. 2006.
P. Gopalakrishnan, X. Li and L. Pileggi, “A Metric-Embedding Inspired Approach to Timing-driven FPGA Placement”, Design Automation Conference, June 2006.
X. Li, J. Le and L. Pileggi, “Projection-Based Statistical Analysis of Full-Chip Leakage Power with Non-Log-Normal Distributions”, Design Automation Conference, June 2006.
T. Jhaveri, L. Pileggi, V. Rovner, A.J. Strojwas, “Maximization of layout printability/manufacturability by extreme layout regularity”, SPIE 31st International Symposium on Microlithography Symposium (invited presentation), February 2006.
L. Pileggi and A.J. Strojwas, “Regular Fabrics for Nano-Scaled CMOS Technologies”, International Solid State Circuits Conference (invited presentation), February 2006.
2005
X. Li, J. Le, L. Pileggi and A.J. Strojwas, “Projection-Based Performance Modeling for Inter/Intra-Die Variations”, Proceedings of the International Conference on Computer-Aided Design, November 2005.
X. Li, J. Le, M. Celik and L. Pileggi, “Defining Statistical Sensitivity for Timing Optimization of Logic Circuits with Large-Scale Process and Environmental Variations”, Proceedings of the International Conference on Computer-Aided Design, November 2005.
X. Li, P. Li and L. Pileggi, “Parameterized Interconnect Order Reduction with Explicit-and-Implicit Multi-Parameter Moment Matching for Inter/Intra-Die Variations”, Proceedings of the International Conference on Computer-Aided Design, November 2005.
X. Li, J. Wang, W. Chiang and L. Pileggi, “Performance-Centering Optimization for System-Level Analog Design Exploration”, Proceedings of the International Conference on Computer-Aided Design, November 2005.
G. Keskin, X. Li and L. Pileggi, “Reducing Power Supply Noise in Integrated Circuits Using Active Resistors”, Proceedings of the SRC Techcon Conference, October 2005.
P. Li, Y. Dong and L. Pileggi, “Temperature-Dependent Optimization of Cache Leakage Power Dissipation”, Proceedings of the International Conference on Computer Design, October 2005.
R. Batra, P. Li, L. Pileggi, W.J. Chiang, “A Behavioral Level Approach for Nonlinear Dynamic Modeling of Voltage-Controlled Oscillators”, Int’l Custom Integrated Circuits Conference, Sept. 2005.
P. Gopalakrishnan and L. Pileggi, “Timing Driven Initial Placement for FPGAs via Graph Matching”, Proceedings of the SRC Techcon Conference, October 2005.
Y. Xu, K. L. Hsiung, L. Pileggi, and S. Boyd, “OPERA: OPtimization with Ellipsoidal uncertainty for Robust Analog IC design”, Design Automation Conference, June 2005.
Y. Zhan, X. Li, A. Strojwas, and L. Pileggi, “Correlation-Aware Statistical Timing Analysis with Non-Gaussian Delay Distributions”, Design Automation Conference, June 2005.
2004
R. Batra, P. Li, Y-T. Chen and L. Pileggi, “A Methodology for Analog Circuit Macromodeling”, IEEE International Workshop on Behavioral Modeling and Simulation, October 2004.
R. Marculescu, D. Marculescu and L. Pileggi, “Toward an Integrated Design Methodology Fault Tolerant”, Multiple Clock/Voltage Integrated Systems, Proceedings of the International Conference on Computer Design, October 2004.
V. Chandra, H. Schmit and L. Pileggi, “A Power Aware System Level Interconnect Design Methodology for Latency-Insensitive”, Proceedings of the International Conference on Computer-Aided Design, November 2004.
P. Li, L. Pileggi, M. Ashegi, R. Chandra, “Efficient Full-Chip Thermal Modeling and Analysis”, Proceedings of the International Conference on Computer-Aided Design, November 2004.
P. Li and L. Pileggi, “Efficient Harmonic Balance Simulation Using Multi-Level Frequency Decomposition”, Proceedings of the International Conference on Computer-Aided Design, November 2004.
X. Li and L. Pileggi, “Robust Analog/RF Circuit Design with Projection-Based Posynomial”, Proceedings of the International Conference on Computer-Aided Design, November 2004.
X. Li, J. Le, P. Gopalakrishnan and L. Pileggi, “Asymptotic Probability Extraction for Non-Normal Distributions of Circuit Performance”, Proceedings of the International Conference on Computer-Aided Design (Best Paper Award), November 2004.
Y. Xu, C. Boone and L. Pileggi, “IEEE Journal of Solid State Circuits”, Volume: 39, Issue: 8, pp. 1347-1351, Aug. 2004.
Yang Xu, Larry Pileggi, Stephan Boyd, “ORACLE: Optimization with Recourse of Analog Circuits including Layout Extraction”, August 2004
Y. Xu, C. Boone and L. Pileggi, “Metal-mask configurable RF Front-end Circuits”, in Proceedings of IEEE RFIC Symposium, June 2004.
2003
P. Li and L. T. Pileggi, “Efficient Per-Nonlinearity Distortion Analysis for Analog and RF Circuits”, IEEE Transactions on Computer-Aided Design, Vol. 22, No. 10, pp. 1297-1309, October 2003.
H. Zheng, B. Krauter and L.T. Pileggi, “Electrical Modeling of Integrated-Package Power/Ground Distributions”, IEEE Design and Test, Volume: 20 Issue: 3, pp. 23-31, May-June 2003.
P. Li and L. Pileggi, “Modeling Nonlinear Communication ICs Using a Multivariate Formulation”, IEEE International Workshop on Behavioral Modeling and Simulation, October 2003.
P. Li, X. Li, Y. Xu and L. Pileggi, “A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits”, Proceedings of the International Conference on Computer-Aided Design, November 2003.
J. Le, A. Devgan and L. Pileggi, “Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics”, Proceedings of the International Conference on Computer-Aided Design, November 2003.
H. Zheng, B. Krauter, L. Pileggi, “On-Package Decoupling Optimization with Package Macromodels”, Int’l Custom Integrated Circuits Conference, Sept. 2003.
K.Y. Tong, V. Kheterapal, S. Rovner, H. Schmit, L. Pileggi, R. Puri, “Regular Logic Fabrics for a Via Patterned Gate Array (VPGA)”, Int’l Custom Integrated Circuits Conference, Sept. 2003.
A. Koorapaty, L. Pileggi, H. Schmit, “Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics”, International Conference on Field Programmable Logic and Applications, September 2003.
S. Gupta and L. Pileggi, “Hierarchical Modeling of Electrostatic and Magnetostatic Coupling”, Proceedings of the SRC Techcon Conference, August 2003.
X. Qi, G. Leonhardt, D. Flees, X-D, Yang, S. Kim, S. Mueller, H. Mau and L. Pileggi, “Simulation Approach for Inductance Effects of VLSI Interconnects”, In Proc. of the Great Lakes Symposium on VLSI, May 2003.
2002
M. Beattie and L.T. Pileggi, “On-Chip Induction Modeling: Basics and Advanced Methods”, Special Issue of IEEE Transactions on VLSI Systems, vol. 10, No. 6, pp. 712-729, December 2002.
M. Celik, H. Zheng and L. Pileggi, “Efficient Reduction of Susceptance-Based Package Models Using PRIMA”, Proceedings of the Topical Meeting on Electrical Performance of Electronic Packaging, October 2002.
H. Zheng and L. Pileggi, “Robust and Passive Model OrderReduction for Circuits Containing Susceptance Elements”, Proceedings of the International Conference on Computer-Aided Design, November 2002.
T. Lin and L. Pileggi, “Throughput Driven IC Communication Synthesis”, Proceedings of the International Conference on Computer-Aided Design, November 2002.
A. Koorapaty and L. Pileggi, Modular, “Fabric-specific Synthesis for Programmable Architectures”, International Conference on Field Programmable Logic and Applications, September 2002, France.
H. Zheng and L. Pileggi, “Modeling and Analysis of Regular Symmetrically Structured Power/Ground Distribution Networks”, ACM/IEEE Design Automation Conference, June 2002.
T. Lin, M. Beattie and L. Pileggi, “On the Efficacy of Simplified 2D On-Chip Inductance Models”, ACM/IEEE Design Automation Conference, June 2002.
R. Arunachalam, R. D. Blanton, L. T. Pileggi, “Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation”, VLSI Design (Special Issue on TimingAnalysis and Optimization for DSM ICs), Vol.15, pp. 605-618, May 2002.
E. Acar, F. Dartu and L. T. Pileggi, “TETA: Transistor level Waveform Evaluation for Timing Analysis”, IEEE Transactions on Computer-Aided Design, Vol. 21, No. 5, May 2002.
D. Pandini, L. Pileggi and A. Strojwas, “Understanding and Addressing the Impact of Wiring Congestion During Technology Mapping”, Int’l Symposium on Physical Design (ISPD), April 2002.
2001
Y-C. Lu, M. Celik, T. Young, and L. Pileggi, “Min/Max On-Chip Inductance Models and Delay Metrics”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
R. Arunachalam, R. D. Blanton and L. Pileggi, “False coupling interactions in static timing analysis”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
M. Beattie, L. Pileggi, “Inductance 101 (Embedded Tutorial)”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
M. Beattie, L. Pileggi, “Modeling Magnetic Coupling for Gigascale Interconnect”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
P. Gopalakrishnan, A. Odabasioglu, L. Pileggi and S. Raje, “Overcoming Wireload Model Uncertainty During Physical Design”, Int’l Symposium on Physical Design (ISPD), April 2001.
T. Lin and L. Pileggi, “RC(L)Interconnect Sizing With Second Order Considerations via Posynomial Programming”, Int’l Symposium on Physical Design (ISPD), April 2001.
Y. Liu, L. T. Pileggi and A.J. Strojwas, “ftd: Frequency to Time Domain Conversion for Reduced Order Interconnect Circuits”, IEEE Transactions on Circuits and Systems, April 2001.
M. Beattie and L. Pileggi, “Efficient Inductance Extraction via Windowing”, Design and Test in Europe Conference (DATE), March 2001.
E. Acar, S. Nassif and L. Pileggi, Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations, Int’l Symposium on Quality in Electronic Design, March 2001.
R.E. Bryant, K.T. Cheng, A.B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. Rabaey and A. Sangiovanni-Vincentelli, “Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI”, Proceedings of the IEEE, Special Issue on the Limits of Semiconductor Technology, pp. 341-366, March 2001.
2000
E. Acar, S. Nassif and L. Pileggi, “Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations”, ACM/IEEE Workshop on Timing in the Specification and Synthesis of Digital Systems, December 2000.
M. Beattie, S. Gupta, L. Pileggi, “Hierarchical Interconnect Circuit Models”, Proceedings of the International Conference on Computer-Aided Design, November 2000.
R. Arunachalam and L.T. Pileggi, “Can We Continue to Predict Timing of ICs Prior to Manufacturing as Technologies Continue to Scale?”, ISD Magazine, September 2000.
T. Lin and L. Pileggi, “RC(L) Interconnect Sizing with Second Order Considerations”, Proceedings of the SRC Techcon Conference, September 2000.
R. Arunachalam, K. Rajagopal and L. Pileggi, “TACO: Timing Analysis with Coupling”, Proceedings of the Design Automation Conference, June 2000.
Y. Liu, S. Nassif, L. Pileggi and A.J. Strojwas, “Impact of interconnect variations on the clock skew of a gigahertz microprocessor”, Proceedings of the Design Automation Conference, June 2000.
1999
M. Beattie and L. Pileggi, “Electromagnetic Parasitic Extraction via a Multipole Method with Hierarchical Refinement”, Proceedings of the International Conference on Computer-Aided Design, November 1999.
A. Odabasioglu, M. Celik & L. T. Pileggi, “Practical Considerations for Passive Reduction of RLC Circuits”, Proceedings of the International Conference on Computer- Aided Design, November 1999.
A. Odabasioglu, M. Celik & L. T. Pileggi, “Efficient and Accurate Delay Metrics for RC Interconnect”, PATMOS: International Workshop on Power and Timing Modeling, Optimization and Simulation, October 1999.
Y. Liu, L. Pileggi and A.J. Strojwas, “Model Order-Reduction of RC(L) Interconnect including Variational Analysis”, Proceedings of the Design Automation Conference (Best Paper Award Nomination), June 1999.
M. Beattie and L. Pileggi, “IC Analyses Including Extracted Inductance Models”, Proceedings of the Design Automation Conference, Invited Paper, June 1999.
L. Pileggi, “Achieving Timing Closure for Giga-Scale IC Designs”, 1999 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Invited Paper, March 1999.
E. Acar, A. Odabasioglu, M. Celik and L. Pileggi, “S2P: Stable 2-Pole Model for RC Interconnect Delay Analysis”, Proceedings of the 9th Great Lakes Symposium on VLSI, March 1999.
M. Celik and L. T. Pileggi, “Metrics and Bounds for Phase Delay and Signal Attenuation in RCL Clock Trees”, IEEE Transactions on Computer-Aided Design, Vol. 18, No. 3, pp. 293-300, March 1999.
M. Beattie and L. T. Pileggi, “Bounds for BEM Capacitance Extraction”, IEEE Transactions on Computer-Aided Design, Vol. 18, No. 3, pp. 311-321, March 1999.
1998
M. Beattie, L. Alatan and L. Pileggi, “Equipotential Shells for Efficient Partial Inductance Extraction”, Proceedings of the International Electronics Devices Meeting, December 1998.
P. Gross, R. Arunachalam, K. Rajagopal and L. Pileggi, “Determination of Worst-Case Aggressor Alignment for Delay Calculation”, Proceedings of the International Conference on Computer-Aided Design, November 1998.
T. Lin, Emrah Acar and L. Pileggi, “h-gamma: An Interconnect Timing Metric Based on the Gamma Distribution Model for the Homogeneous Response”, Proceedings of the International Conference on Computer-Aided Design, November 1998.
T. Lin and L. Pileggi, “Looking Beyond the Elmore Delay — Metrics for Deep Submicron”, Proceedings of the SRC Techcon Conference, September 1998.
M. Beattie and L. Pileggi, “Equipotential Shells for Efficient Inductance Extraction”, Proceedings of the SRC Techcon Conference, September 1998.
F. Liu, L. Pileggi and A.J. Strojwas, “A Synthesized Driving-Point Model for Capacitively Coupled Interconnects”, Proceedings of the SRC Techcon Conference, September 1998.
K. Rajagopal, P. Gross and L. Pileggi, “The Impact of Coupling on Worst-Case Waveform Analysis”, Proceedings of the SRC Techcon Conference, September 1998.
Rohini Gupta, John Willis and L.T. Pileggi, “Analytic Termination Metrics for Pin-to- Pin Lossy Transmission Lines with Nonlinear Drivers”, IEEE Transactions on VLSI Systems, Vol. 6, No. 3, pp. 457-463, September 1998.
A. Odabasioglu, M. Celik and L. T. Pileggi, “PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm”, IEEE Transactions on Computer-Aided Design (1999 IEEE Best Paper Award), Vol. 17, No. 8, pp. 645-654, August 1998.
R. Kay and L. Pileggi, EWA: “Efficient Wire Sizing Algorithm”, IEEE Transactions on Computer-Aided Design, January, 1998.
1997
N. Menezes, R. Baldick and L.T. Pileggi, “A Sequential Quadratic Programming Approach to Concurrent Gate and Interconnect Sizing”, IEEE Transactions on Computer- Aided Design, August 1997.
G. Ellis, L.T. Pileggi, R.A. Rutenbar, “A Hierarchical Decomposition Methodology for Multistage Clock Circuits”, Proceedings of the International Conference on Computer-Aided Design, 1997.
A. Odabasioglu, M. Celik, L.T. Pileggi, “PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm”, Proceedings of the International Conference on Computer-Aided Design, 1997.
A. Mehta, Y-P. Chen, N. Menezes, L. T.Pileggi and M. Wong, “Clustering and Load Balancing for Buffered Clock Tree Synthesis”, Proceedings of the Int’l Conference on Computer Design, October 1997.
Ravishankar Arunachalam, Florentin Dartu and Lawrence T.Pileggi, “CMOS Gate Delay Models for General RLC Loading”, Proceedings of the Int’l Conference on Computer Design, October 1997.
John He, Mustafa Celik and Lawrence Pileggi, “SPIE: Sparse PEEC Inductance Extraction”, Proceedings of the Design Automation Conference, 1997.
Michael Beattie and Lawrence Pileggi, “Bounds for BEM Capacitance Extraction”, Proceedings of the Design Automation Conference, 1997.
Florin Dartu and Lawrence Pileggi, “Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling”, Proceedings of the Design Automation Conference, 1997.
R. Kay, G. Bucheuv, and L. Pileggi, “EWA: Exact Wire Sizing Algorithm”, 1997 International Symposium on Physical Design, April 1997.
G. Ellis, L. Pileggi and R. Rutenbar, “A Hierarchical Decomposition Methodology for Single-Stage Clock Circuits”, Proceedings of the Custom Integrated Circuits Conference, May 1997.
1996
F. Dartu and L.T. Pileggi, “Gate-level modeling of of coupling capacitance effects”, Proceedings of the SRC Techcon Conference, October 1996.
Florentin Dartu and Lawrence T. Pileggi, “Modeling Signal Waveshapes for Empirical CMOS Gate Delay Models”, Sixth International Workshop on Power and Timing Modeling, Optimization and Simulation, September 1996.
Florin Dartu, Bogdan Tutuianu and Lawrence T. Pileggi, “RC-Interconnect Macromodels for Timing Simulation”, Proceedings of the Design Automation Conference , 1996.
Rohini Gupta and Lawrence Pileggi, “Modeling Lossy Transmission lines Using the Method of Characteristics”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 43, No. 7, pp. 580-583, July 1996.
S. Pullela, N. Menezes and L.T. Pileggi, “Post-Processing of Clock Trees via Wiresizing and Buffering for Robust Design”, IEEE Transactions on Computer-Aided Design, pp. 691-701, June 1996.
Rohini Gupta, John Willis and Lawrence T. Pileggi, “Low Power Design of Off-Chip Drivers and Transmission lines: A Branch and Bound Approach”, International Journal of High Speed Electronics and Systems, Vol. 7, no. 9, pp. 27-45, June 1996.
Bogdan Tutuianu and Lawrence Pileggi, “An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response”, Proceedings of the Design Automation Conference , 1996.
Byron Krauter, Yu Xia, Aykut Dengi, Lawrence T. Pileggi, “A Sparse Image Method for BEM Capacitance Extraction”, Proceedings of the Design Automation Conference, 1996.
Xun Yang, Byron Krauter and L. Pileggi, “Combined ac and Transient Power Distribution Analysis”, Proceedings of the Custom Integrated Circuits Conference, May 1996.
F. Dartu, N. Menezes and L.T. Pileggi, “Performance Computation for Pre-characterized CMOS Gates with RC Loads”, IEEE Transactions on Computer-Aided Design, pp. 544-553, May 1996.
1995
M. Kamon, B. Krauter, J. Phillips, L. Pileggi, and J. White, “Two Optimizations to Accelerated Method-of-Moments Algorithms for Signal Integrity Analysis of Complicated 3-D Packages”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, November 1995.
R. Gupta, B. Krauter, B. Tutuianu, J. Willis and L. Pileggi, “The Elmore Delay as a Bound for RC-Trees with Generalized Input Signals”, Proceedings of the Design Automation Conference, 1995.
R. Gupta and L. Pileggi, “Constrained Multivariable Optimization of Transmission Lines with General Topologies”, Proceedings of the International Conference on Computer-Aided Design, 1995.
N. Menezes, R. Baldick and L. Pileggi, “A Sequential Quadratic Programming Approach to Concurrent Gate and Wire Sizing”, Proceedings of the International Conference on Computer-Aided Design, 1995.
B. Krauter and L. Pileggi, “Generating Sparse Partial Inductance Matrices with Guaranteed Stability”, Proceedings of the International Conference on Computer-Aided Design, 1995.
L. Pileggi, “Coping with RC(L) Interconnect Induced Headaches”, Proceedings of the International Conference on Computer-Aided Design, (Invited Tutorial Paper) 1995.
I. Tesu and L. Pileggi, “Pre-characterization of ECL Gates for Timing Analysis”, SCS ’95 International Symposium on Signals, Circuits & Systems, Iasi, Romania, October 1995.
I. Tesu and L. Pileggi, “Timing Analysis Models for Gates and Cells with Bipolar Transistor Output Stages”, Proceedings of the IEEE ASIC Conference, 1995.
B. Krauter, R. Gupta, J. Willis and L. Pileggi, “Transmission Line Synthesis”, Proceedings of the Design Automation Conference , 1995.
N. Menezes, S. Pullela and L. Pileggi, “Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization”, Proceedings of the Design Automation Conference, 1995.
1994
J. Qian, S. Pullela and L.T. Pillage, Modeling the “Effective Capacitance” of RC Interconnect, IEEE Transactions on Computer-Aided Design, pp. 1526-1535, December 1994.
L.T. Pillage and R.A. Rohrer, “The Essence of AWE”, Circuits and Devices Magazine, November 1994.
John Willis, Rohini Gupta and L.T. Pillage, “Metrics for RLC Transmission Line Termination”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, November 1994.
N. Menezes, S. Pullela and L.T. Pillage, “RC Interconnect Synthesis — A Moment Fitting Approach”, Proceedings of the 1994 International Conference on Computer-Aided Design, Nov. 1994.
R. Gupta, S.Y. Kim and L.T. Pillage, “Domain Characterization of Transmission Line Models for Efficient Simulation”, Proceedings of the International Conference on Computer Design, October 1994.
S.Y. Kim, N. Gopal and L.T. Pillage, “Time-Domain Macromodels for VLSI Interconnect Analysis”, IEEE Transactions on Computer-Aided Design, pp. 1257-1270, October 1994.
R. Gupta and L.T. Pillage, “OTTER: Optimal Termination of Transmission Lines Excluding Radiation”, Proceedings Design Automation Conference, June 1994.
F. Dartu, N. Menezes, J. Qian and L.T. Pillage, “A Gate Delay Model for High Performance CMOS”, Proceedings Design Automation Conference, June 1994.
C. Ratzlaff and L.T. Pillage, “RICE: Rapid Interconnect Circuit Evaluation Using Asymptotic Waveform Evaluation”, IEEE Transactions on Computer-Aided Design, pp. 763-776, June 1994.
D.F. Anastaskis, N. Gopal, S.Y. Kim and L.T. Pillage, “On the Stability of Moment- Matching Approximations in Asymptotic Waveform Evaluation”, IEEE Transactions on Computer-Aided Design, pp. 729-736, June 1994.
1993
S. Y. Kim, E. Tuncer, R. Gupta, B. Krauter, T.L. Savarino, D. P. Neikirk and L. T. Pillage, “An Efficient Methodology for Extraction and Simulation of Transmission Lines for Application Specific Electronic Modules”, Proceedings of the 1993 International Conference on Computer-Aided Design, Nov. 1993.
S. Pullela, N. Menezes and L.T. Pillage, “Skew and Delay Optimization for Reliable Buffered Clock Trees”, Proceedings of the 1993 International Conference on Computer-Aided Design, Nov. 1993.
E. Tuncer, S.Y. Kim, L.T. Pillage and D. Neikirk, A New, “Efficient Circuit Model for Microstrip Lines Including Both Current Crowding and Skin Depth Effects”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, October 1993.
D.C. Yuan, L.T. Pillage, and J.T. Rahmeh, “Evaluation by Parts of Mixed-Level dc- Connected Components in Logic Simulation”, Proceedings Design Automation Conference, June 1993.
S. Pullela, N. Menezes and L.T. Pillage, “Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization”, Proceedings Design Automation Conference, June 1993.
N. Menezes, S. Pullela, A. Balivada and L.T. Pillage, “Skew Reduction in Clock Trees Using Wire Width Optimization”, Proceedings Custom Integrated Circuits Conference, May 1993.
V. Raghavan, R.A. Rohrer, L.T. Pillage, J.Y. Lee, J.E. Braken, M.M. Alaybeyi, AWE-Inspired, “Proceedings Custom Integrated Circuits Conference”, (Invited Tutorial Paper), May 1993.
S.Y. Kim, N. Gopal and L.T. Pillage, “Finite-Pole Macromodels of Transmission Lines for Circuit Simulation”, Proceedings Custom Integrated Circuits Conference, May 1993.
Lawrence T. Pillage, “An Early Introduction to Circuit Simulation Techniques, IEEE Transactions on Education”, February 1993.
1992
R. Brashear, D. Holberg, M.R. Mercer and L.T. Pillage, “ETA: Electrical-Level Timing Analysis”, Proceedings IEEE International Conference on Computer-Aided Design, November 1992.
S.Y. Kim, N. Gopal and L.T. Pillage, “AWE Macromodels for Incorporation in a Circuit Simulator”, Proceedings IEEE International Conference on Computer-Aided Design, November 1992.
M. Becker, D. Beer, M.J. Gonzalez, C.M. Maziar, L.T. Pillage, M.D. Shermis, T.J. Wagner, G.L. Wise, “Introduction to Electrical and Computer Engineering”, Proceedings of the 1992 American Society on Engineering Education Annual Conference, November 1992
D. F. Anastasakis, N. Gopal, S.Y. Kim and L.T. Pillage, “On the Stability of Moment Matching Approximations in Asymptotic Waveform Evaluation”, Proceedings Design Automation Conference, June 1992.
C. Ratzlaff, S. Pullela and L.T. Pillage, “Effects of RC-Interconnect in a Hierarchical Timing Analyzer”, Proceedings Custom Integrated Circuits Conference, May 1992.
N. Gopal, E. Tuncer, D. Neikirk and L.T. Pillage, “Non-Uniform Models for Transmission Line Analysis”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, April, 1992.
1991
N. Gopal, D. Neikirk and L.T. Pillage, “Evaluating RC Interconnect Using Moment Methods” Proceedings IEEE International Conference on Computer-Aided Design, November 1991.
N. Gopal, C. Ratzlaff, L.T. Pillage, “Constrained Approximation of Dominant Time Constants in RC Circuit Delay Models”, Proceedings of the International Mathematics and Computation Symposium, (Invited Paper), July 1991.
C. Ratzlaff, N. Gopal, L.T. Pillage, “RICE: Rapid Interconnect Circuit Evaluator”, Proceedings Design Automation Conference, (Best Paper Award Nomination), June 1991.
A. Balivada, D. Holberg and L.T. Pillage, “Calculation and Application of Time-Domain Sensitivities in Asymptotic Waveform Evaluation”, Proceedings Custom Integrated Circuits Conference, May 1991.
1990
D. Holberg, S. Dutta and L.T. Pillage, “DC Parametrized Piecewise Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation”, Proceedings IEEE International Conference on Computer-Aided Design, November 1990.
S. Dutta and L.T. Pillage, “Calculating the Moments in AWE With Linear Complexity”, Proceedings of the SRC Techcon Conference, October 1990.
L.T. Pillage and S. Dutta, “A Path Tracing Algorithm for Asymptotic Waveform Evaluation of RLC Circuit Delay Models”, 1990 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, August 1990.
L.T. Pillage, X. Huang and R.A. Rohrer, “Asymptotic Waveform Evaluation for Circuits Containing Floating Nodes”, Proceedings IEEE International Symposium on Circuits and Systems, May 1990.
L.T. Pillage and R.A. Rohrer, “Asymptotic Waveform Evaluation”, IEEE Transactions on Computer-Aided Design (1991 IEEE Best Paper Award), pp. 352-366, April 1990.
1989
L.T. Pillage, X. Zhang and R.A. Rohrer, “Efficient Final Placement Based on Nets-as- Points”, Proceedings Design Automation Conference, June 1989.
L.T. Pillage, X. Huang and R.A. Rohrer, “AWEsim: Asymptotic Waveform Evaluation for Timing Analysis”, Proceedings Design Automation Conference, June 1989.
L.T. Pillage, C. Wolff and R.A. Rohrer, “Frequency Response Simulation”, Proceedings Custom Integrated Circuits Conference, May 1989.
L.T. Pillage and R.A. Rohrer, “Delay Evaluation with Lumped Linear RLC Interconnect Circuit Models”, Proceedings Decennial Caltech Conference on VLSI, March 1989.
1988
L.T. Pillage and R.A. Rohrer, “A Quadratic Metric for the Initial Placement Problem with a Simple Solution Scheme”, Proceedings Design Automation Conference, June 1988.
1987
L.T. Pillage, X. Huang and R.A. Rohrer, “TALISMAN: A Piecewise Linear Circuit Simulator Based on Tree Link Analysis”, Proceedings IEEE International Conference on Computer-Aided Design, November 1987.
L.T. Pillage, X. Huang and R.A. Rohrer, “Tree Link Partitioning for the Implicit Solution of Circuits”, Proceedings IEEE International Symposium on Circuits and Systems, May 1987.
