Evaluating Feasibility within Power Flow
Jereminov, D.M. Bromberg, A. Pandey, M.R. Wagner, and L. Pileggi, “Evaluating Feasibility within Power Flow,” IEEE Transactions on Smart Grid, Vol. 11, No. 4, July 2020. DOI: 10.1109/TSG.2020.2966930.
Logic IP for Low-Cost IC Design in Advanced CMOS Nodes
/in Integrated Circuits, Peer Reviewed, Publications /by awpM. Isgenc, M. Martins, S. Pagliarini and L. Pileggi, “Logic IP for Low-Cost IC Design in Advanced CMOS Nodes,” IEEE Transactions on Very Large Scale Integration, Vol 28, Issue 2, February 2020. (DOI:10.1109/TVLSI.2019.2942825.)
Steady-State Simulation for Combined Transmission and Distribution Systems
/in Peer Reviewed, Power Systems, Publications /by awpA. Pandey and L. Pileggi, “Steady-State Simulation for Combined Transmission and Distribution Systems,” in IEEE Transactions on Smart Grid, Vol 11, Issue 2, March 2020. (DOI: 10.1109/TSG.2019.2932403).
From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration
/in Integrated Circuits, Peer Reviewed, Publications /by awpS. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 39, Issue 2, February 2020. DOI (10.1109/TCAD.2018.2889772)
Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography
/in Integrated Circuits, Peer Reviewed, Publications, Secure Hardware /by awpI. Karageorgos, M. Isgenc, S. Pagliarini, and L. Pileggi, Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography, Journal of Hardware and Systems Security, November 2019 (DOI: 10.1007/s41635-019-00080-y).
Latch-Based Logic Locking
/in Conference, Publications, Secure Hardware /by awpJ. Sweeney, M. Zackriya, S. Pagliarini, and L. Pileggi, “Latch-Based Logic Locking,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2020.
Latch-Based Logic Locking
/in Conference, Publications, Secure Hardware /by awpJ. Sweeney, M. Zackriya, S. Pagliarini, and L. Pileggi, “Latch-Based Logic Locking,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 2020.
Logic IP for Low-Cost IC Design in Advanced CMOS Nodes
/in Conference, Integrated Circuits, Publications /by awpM. Isgenc, M. Martins, S. Pagliarini and L. Pileggi, “Logic IP for Low-Cost IC Design in Advanced CMOS Nodes,” IEEE Transactions on Very Large Scale Integration, Vol 28, Issue 2, February 2020. (DOI:10.1109/TVLSI.2019.2942825.)
Steady-State Simulation for Combined Transmission and Distribution Systems
/in Conference, Power Systems, Publications /by awpA. Pandey and L. Pileggi, “Steady-State Simulation for Combined Transmission and Distribution Systems,” in IEEE Transactions on Smart Grid, August 2019. (DOI: 10.1109/TSG.2019.2932403)
From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration
/in Conference, Integrated Circuits, Publications /by awpS. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 39, Issue 2, February 2020. DOI (10.1109/TCAD.2018.2889772)
Contact
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774