Wire Width Optimization of Transmission Lines for Low Power Design
Rohini Gupta, John Willis and L.T. Pillage, “Wire Width Optimization of Transmission Lines for Low Power Design”, IEEE Multi-chip Module Conference, February 1995.
This author has yet to write their bio.Meanwhile lets just say that we are proud awp contributed a whooping 434 entries.
Rohini Gupta, John Willis and L.T. Pillage, “Wire Width Optimization of Transmission Lines for Low Power Design”, IEEE Multi-chip Module Conference, February 1995.
J. Qian, S. Pullela and L.T. Pillage, Modeling the “Effective Capacitance” of RC Interconnect, IEEE Transactions on Computer-Aided Design, pp. 1526-1535, December 1994.
N. Menezes, S. Pullela and L.T. Pillage, “RC Interconnect Synthesis — A Moment Fitting Approach”, Proceedings of the 1994 International Conference on Computer-Aided Design, Nov. 1994.
John Willis, Rohini Gupta and L.T. Pillage, “Metrics for RLC Transmission Line Termination”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, November 1994.
L.T. Pillage and R.A. Rohrer, “The Essence of AWE”, Circuits and Devices Magazine, November 1994.
R. Gupta, S.Y. Kim and L.T. Pillage, “Domain Characterization of Transmission Line Models for Efficient Simulation”, Proceedings of the International Conference on Computer Design, October 1994.
S.Y. Kim, N. Gopal and L.T. Pillage, “Time-Domain Macromodels for VLSI Interconnect Analysis”, IEEE Transactions on Computer-Aided Design, pp. 1257-1270, October 1994.
F. Dartu, N. Menezes, J. Qian and L.T. Pillage, “A Gate Delay Model for High Performance CMOS”, Proceedings Design Automation Conference, June 1994.
R. Gupta and L.T. Pillage, “OTTER: Optimal Termination of Transmission Lines Excluding Radiation”, Proceedings Design Automation Conference, June 1994.
D.F. Anastaskis, N. Gopal, S.Y. Kim and L.T. Pillage, “On the Stability of Moment- Matching Approximations in Asymptotic Waveform Evaluation”, IEEE Transactions on Computer-Aided Design, pp. 729-736, June 1994.
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