Timing Metrics for Physical Design of Deep Submicron Technologies
L. Pileggi, “Timing Metrics for Physical Design of Deep Submicron Technologies”, Invited paper, International Symposium on Physical Design, April 1998.
A Simple Algorithm for Calculating Frequency-Dependent Inductance Bounds
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpZhijiang (John) He and Lawrence T. Pileggi, “A Simple Algorithm for Calculating Frequency-Dependent Inductance Bounds”, Proceedings of the Custom Integrated Circuits Conference, May 1998.
Simulation of Lossy Multiconductor Transmission Lines Using Backward Euler
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpM. Celik and L. T. Pileggi, “Simulation of Lossy Multiconductor Transmission Lines Using Backward Euler”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 45, No. 3, pp. 238-243, March 1998.
A Sequential Quadratic Programming Approach to Concurrent Gate and Interconnect Sizing
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpN. Menezes, R. Baldick and L.T. Pileggi, “A Sequential Quadratic Programming Approach to Concurrent Gate and Interconnect Sizing”, IEEE Transactions on Computer- Aided Design, August 1997.
A Hierarchical Decomposition Methodology for Multistage Clock Circuits
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpG. Ellis, L.T. Pileggi, R.A. Rutenbar, “A Hierarchical Decomposition Methodology for Multistage Clock Circuits”, Proceedings of the International Conference on Computer-Aided Design, 1997.
PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpA. Odabasioglu, M. Celik, L.T. Pileggi, “PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm”, Proceedings of the International Conference on Computer-Aided Design, 1997.
Clustering and Load Balancing for Buffered Clock Tree Synthesis
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpA. Mehta, Y-P. Chen, N. Menezes, L. T.Pileggi and M. Wong, “Clustering and Load Balancing for Buffered Clock Tree Synthesis”, Proceedings of the Int’l Conference on Computer Design, October 1997.
CMOS Gate Delay Models for General RLC Loading
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpRavishankar Arunachalam, Florentin Dartu and Lawrence T.Pileggi, “CMOS Gate Delay Models for General RLC Loading”, Proceedings of the Int’l Conference on Computer Design, October 1997.
SPIE: Sparse PEEC Inductance Extraction
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpJohn He, Mustafa Celik and Lawrence Pileggi, “SPIE: Sparse PEEC Inductance Extraction”, Proceedings of the Design Automation Conference, 1997.
Bounds for BEM Capacitance Extraction
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpMichael Beattie and Lawrence Pileggi, “Bounds for BEM Capacitance Extraction”, Proceedings of the Design Automation Conference, 1997.
Contact
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774