T. Lin and L. Pileggi, “RC(L)Interconnect Sizing With Second Order Considerations via Posynomial Programming”, Int’l Symposium on Physical Design (ISPD), April 2001.
Y. Liu, L. T. Pileggi and A.J. Strojwas, “ftd: Frequency to Time Domain Conversion for Reduced Order Interconnect Circuits”, IEEE Transactions on Circuits and Systems, April 2001.
M. Beattie and L. Pileggi, “Efficient Inductance Extraction via Windowing”, Design and Test in Europe Conference (DATE), March 2001.
E. Acar, S. Nassif and L. Pileggi, Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations, Int’l Symposium on Quality in Electronic Design, March 2001.
R.E. Bryant, K.T. Cheng, A.B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. Rabaey and A. Sangiovanni-Vincentelli, “Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI”, Proceedings of the IEEE, Special Issue on the Limits of Semiconductor Technology, pp. 341-366, March 2001.
M. Beattie, B. Krauter, L. Alatan and L. Pileggi, “Equipotential Shells for Efficient Inductance Extraction”, IEEE Transactions on Computer-Aided Design, Vol. 20, No. 1, January 2001.
E. Acar, S. Nassif and L. Pileggi, “Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations”, ACM/IEEE Workshop on Timing in the Specification and Synthesis of Digital Systems, December 2000.
M. Beattie, S. Gupta, L. Pileggi, “Hierarchical Interconnect Circuit Models”, Proceedings of the International Conference on Computer-Aided Design, November 2000.
T. Lin and L. Pileggi, “RC(L) Interconnect Sizing with Second Order Considerations”, Proceedings of the SRC Techcon Conference, September 2000.
R. Arunachalam and L.T. Pileggi, “Can We Continue to Predict Timing of ICs Prior to Manufacturing as Technologies Continue to Scale?”, ISD Magazine, September 2000.
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774