Modeling and Analysis of Regular Symmetrically Structured Power/Ground Distribution Networks

H. Zheng and L. Pileggi, “Modeling and Analysis of Regular Symmetrically Structured Power/Ground Distribution Networks”, ACM/IEEE Design Automation Conference, June 2002.

TETA: Transistor level Waveform Evaluation for Timing Analysis

E. Acar, F. Dartu and L. T. Pileggi, “TETA: Transistor level Waveform Evaluation for Timing Analysis”, IEEE Transactions on Computer-Aided Design, Vol. 21, No. 5, May 2002.

Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation

R. Arunachalam, R. D. Blanton, L. T. Pileggi, “Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation”, VLSI Design (Special Issue on TimingAnalysis and Optimization for DSM ICs), Vol.15, pp. 605-618, May 2002.

Understanding and Addressing the Impact of Wiring Congestion During Technology Mapping

D. Pandini, L. Pileggi and A. Strojwas, “Understanding and Addressing the Impact of Wiring Congestion During Technology Mapping”, Int’l Symposium on Physical Design (ISPD), April 2002.

Congestion-Aware Logic Synthesis

D. Pandini, L. Pileggi and A. Strojwas, “Congestion-Aware Logic Synthesis”, Design and Test in Europe Conference (DATE), March 2002.

A Linear-Centric Modeling Approach to Harmonic Balance Analysis

P. Li and L. Pileggi, “A Linear-Centric Modeling Approach to Harmonic Balance Analysis”, Design and Test in Europe Conference (DATE), March 2002.

On-Chip Inductance Models:3D or not 3D?

T. Lin, M. Beattie and L. Pileggi, “On-Chip Inductance Models:3D or not 3D?”, Design and Test in Europe Conference (DATE), March 2002.

A Linear-Centric Simulation Framework for Parametric Fluctuations

E. Acar, L. Pileggi and S. Nassif, “A Linear-Centric Simulation Framework for Parametric Fluctuations”, Design and Test in Europe Conference (DATE), March 2002.

Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses

H. Zhang, B. Krauter, M. Beattie and L. Pileggi, “Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses”, Design and Test in Europe Conference (DATE), March 2002.

Time-Domain Simulation of Variational Interconnect Models

E. Acar, S. Nassif and L. Pileggi, “Time-Domain Simulation of Variational Interconnect Models”, Int’l Symposium on Quality in Electronic Design, March 2002.