V. Chandra, A. Xu, H. Schmit and L. Pileggi, “An Interconnect Channel Design Methodology for High Performance Integrated Circuits”, Design and Test in Europe Conference (DATE), February 2004.
M. Beattie and L.T. Pileggi, “Parasitic Extraction with Multipole Refinement”, IEEE Transactions on Computer-Aided Design, Vol. 23, (5 pages), February 2004.
P. Li and L. T. Pileggi, “Efficient Per-Nonlinearity Distortion Analysis for Analog and RF Circuits”, IEEE Transactions on Computer-Aided Design, Vol. 22, No. 10, pp. 1297-1309, October 2003.
H. Zheng, B. Krauter and L.T. Pileggi, “Electrical Modeling of Integrated-Package Power/Ground Distributions”, IEEE Design and Test, Volume: 20 Issue: 3, pp. 23-31, May-June 2003.
P. Li and L. Pileggi, “Modeling Nonlinear Communication ICs Using a Multivariate Formulation”, IEEE International Workshop on Behavioral Modeling and Simulation, October 2003.
P. Li, X. Li, Y. Xu and L. Pileggi, “A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits”, Proceedings of the International Conference on Computer-Aided Design, November 2003.
J. Le, A. Devgan and L. Pileggi, “Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics”, Proceedings of the International Conference on Computer-Aided Design, November 2003.
H. Zheng, B. Krauter, L. Pileggi, “On-Package Decoupling Optimization with Package Macromodels”, Int’l Custom Integrated Circuits Conference, Sept. 2003.
K.Y. Tong, V. Kheterapal, S. Rovner, H. Schmit, L. Pileggi, R. Puri, “Regular Logic Fabrics for a Via Patterned Gate Array (VPGA)”, Int’l Custom Integrated Circuits Conference, Sept. 2003.
A. Koorapaty, L. Pileggi, H. Schmit, “Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics”, International Conference on Field Programmable Logic and Applications, September 2003.
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774