All-Magnetic, Nonvolatile, Addressable Chainlink Memory
D. Bromberg, D. Morris, L. Pileggi and J. Zhu, “All-Magnetic, Nonvolatile, Addressable Chainlink Memory”, IEEE Transactions on Magnetics, vol. 49, no. 7, 2013.
Efficient System-Level Performance Modeling and Optimization for Reprogrammable Radio Frequency (RF) Systems
/0 Comments/in Conference, Publications, Secure Hardware /by awpJ. Tao, Y-C. Wang, M. Jun, X. Li, R. Negi, T. Mukherjee and L. Pileggi, “Efficient System-Level Performance Modeling and Optimization for Reprogrammable Radio Frequency (RF) Systems”, Frontiers in Analog CAD Workshop, February 2013.
Naturally Oxidized FeCo as a Magnetic Coupling Layer for Electrically Isolated Read/Write Paths in mLogic
/0 Comments/in Integrated Circuits, Peer Reviewed, Publications /by awpV. Sokalski, D. Bromberg, D. Morris, M. T. Moneck, E. Yang, L. Pileggi, and J-G. Zhu, “Naturally Oxidized FeCo as a Magnetic Coupling Layer for Electrically Isolated Read/Write Paths in mLogic”, IEEE Transactions on Magnetics, vol. 49, no. 7, 2013.
Trusted Split-Fabrication System-on-Chip Design Technology and Methodology
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpE. Sumbul, A. Patterson, G. Fedder, F. Franchetti, G. Piazza and L. Pileggi, “Trusted Split-Fabrication System-on-Chip Design Technology and Methodology”, (Invited Paper) GOMACTech Technical Program, March 2013.
Rethinking ASIC design with next-generation lithography and process integration
/0 Comments/in Conference, Integrated Circuits, Publications /by awpK. Vaidyanathan, L. Liebmann and L. Pileggi, “Rethinking ASIC design with next-generation lithography and process integration”, SPIE Advanced Lithography Conference, February 2013.
Naturally Oxidized FeCo as a Magnetic Coupling Layer for Electrically Isolated Read/Write Paths in mLogic
/0 Comments/in Conference, Integrated Circuits, Publications /by awpV. Sokalski, D.M. Bromberg, D. Morris, M.T. Moneck, E. Yang, L. Pileggi, J-G. Zhu, “Naturally Oxidized FeCo as a Magnetic Coupling Layer for Electrically Isolated Read/Write Paths in mLogic”, 12th Joint MMM/Intermag Conference, January 2013.
All-Magnetic, Nonvolatile, Addressable Chainlink Memory
/0 Comments/in Conference, Integrated Circuits, Publications /by awpD. Bromberg, D. Morris, L. Pileggi and J. Zhu, “All-Magnetic, Nonvolatile, Addressable Chainlink Memory”, 12th Joint MMM/Intermag Conference, January 2013.
Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpQ. Zhu, C. Berger, E. Turner, L. Pileggi and F. Franchetti, “Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation”, Journal of Signal Processing Systems, 2012.
Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography
/in Conference, Integrated Circuits, Publications /by awpQ. Zhu, L. Pileggi and F. Franchetti, Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography, Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October 2012.
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
/0 Comments/in Conference, Integrated Circuits, Publications /by awpJ.-O. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakani, S. Yaldiz, L. Pileggi, R. Harjani, S. Reynolds, J. A. Tierno, D. Friedman, “A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS”, Int’l Custom Integrated Circuits Conference, Sept. 2012.
Contact
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774