A Synthesized Driving-Point Model for Capacitively Coupled Interconnects
F. Liu, L. Pileggi and A.J. Strojwas, “A Synthesized Driving-Point Model for Capacitively Coupled Interconnects”, Proceedings of the SRC Techcon Conference, September 1998.
The Impact of Coupling on Worst-Case Waveform Analysis
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpK. Rajagopal, P. Gross and L. Pileggi, “The Impact of Coupling on Worst-Case Waveform Analysis”, Proceedings of the SRC Techcon Conference, September 1998.
Looking Beyond the Elmore Delay — Metrics for Deep Submicron
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpT. Lin and L. Pileggi, “Looking Beyond the Elmore Delay — Metrics for Deep Submicron”, Proceedings of the SRC Techcon Conference, September 1998.
Equipotential Shells for Efficient Inductance Extraction
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpM. Beattie and L. Pileggi, “Equipotential Shells for Efficient Inductance Extraction”, Proceedings of the SRC Techcon Conference, September 1998.
Analytic Termination Metrics for Pin-to- Pin Lossy Transmission Lines with Nonlinear Drivers
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpRohini Gupta, John Willis and L.T. Pileggi, “Analytic Termination Metrics for Pin-to- Pin Lossy Transmission Lines with Nonlinear Drivers”, IEEE Transactions on VLSI Systems, Vol. 6, No. 3, pp. 457-463, September 1998.
PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpA. Odabasioglu, M. Celik and L. T. Pileggi, “PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm”, IEEE Transactions on Computer-Aided Design (1999 IEEE Best Paper Award), Vol. 17, No. 8, pp. 645-654, August 1998.
Efficient Wire Sizing Algorithm
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpR. Kay and L. Pileggi, EWA: “Efficient Wire Sizing Algorithm”, IEEE Transactions on Computer-Aided Design, January, 1998.
TETA: Transistor-Level Engine for Timing Analysis
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpFlorin Dartu and Lawrence Pileggi, “TETA: Transistor-Level Engine for Timing Analysis”, Proceedings of the Design Automation Conference, June 1998.
An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpFrank Liu, Lawrence Pileggi and Andrzej Strojwas, ftd: “An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models”, Proceedings of the Design Automation Conference, June 1998.
PRIMO: Probability Interpretation of Moments for Delay Calculation
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpRony Kay and Lawrence Pileggi, “PRIMO: Probability Interpretation of Moments for Delay Calculation”, Proceedings of the Design Automation Conference, June 1998.
Contact
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774