Equipotential Shells for Efficient Partial Inductance Extraction

M. Beattie, L. Alatan and L. Pileggi, “Equipotential Shells for Efficient Partial Inductance Extraction”, Proceedings of the International Electronics Devices Meeting, December 1998.

Determination of Worst-Case Aggressor Alignment for Delay Calculation

P. Gross, R. Arunachalam, K. Rajagopal and L. Pileggi, “Determination of Worst-Case Aggressor Alignment for Delay Calculation”, Proceedings of the International Conference on Computer-Aided Design, November 1998.

h-gamma: An Interconnect Timing Metric Based on the Gamma Distribution Model for the Homogeneous Response

T. Lin, Emrah Acar and L. Pileggi, “h-gamma: An Interconnect Timing Metric Based on the Gamma Distribution Model for the Homogeneous Response”, Proceedings of the International Conference on Computer-Aided Design, November 1998.

A Synthesized Driving-Point Model for Capacitively Coupled Interconnects

F. Liu, L. Pileggi and A.J. Strojwas, “A Synthesized Driving-Point Model for Capacitively Coupled Interconnects”, Proceedings of the SRC Techcon Conference, September 1998.

The Impact of Coupling on Worst-Case Waveform Analysis

K. Rajagopal, P. Gross and L. Pileggi, “The Impact of Coupling on Worst-Case Waveform Analysis”, Proceedings of the SRC Techcon Conference, September 1998.

Looking Beyond the Elmore Delay — Metrics for Deep Submicron

T. Lin and L. Pileggi, “Looking Beyond the Elmore Delay — Metrics for Deep Submicron”, Proceedings of the SRC Techcon Conference, September 1998.

Equipotential Shells for Efficient Inductance Extraction

M. Beattie and L. Pileggi, “Equipotential Shells for Efficient Inductance Extraction”, Proceedings of the SRC Techcon Conference, September 1998.

PRIMO: Probability Interpretation of Moments for Delay Calculation

Rony Kay and Lawrence Pileggi, “PRIMO: Probability Interpretation of Moments for Delay Calculation”, Proceedings of the Design Automation Conference, June 1998.

TETA: Transistor-Level Engine for Timing Analysis

Florin Dartu and Lawrence Pileggi, “TETA: Transistor-Level Engine for Timing Analysis”, Proceedings of the Design Automation Conference, June 1998.

An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models

Frank Liu, Lawrence Pileggi and Andrzej Strojwas, ftd: “An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models”, Proceedings of the Design Automation Conference, June 1998.