RC(L) Interconnect Sizing with Second Order Considerations

T. Lin and L. Pileggi, “RC(L) Interconnect Sizing with Second Order Considerations”, Proceedings of the SRC Techcon Conference, September 2000.

TACO: Timing Analysis with Coupling

R. Arunachalam, K. Rajagopal and L. Pileggi, “TACO: Timing Analysis with Coupling”, Proceedings of the Design Automation Conference, June 2000.

Impact of interconnect variations on the clock skew of a gigahertz microprocessor

Y. Liu, S. Nassif, L. Pileggi and A.J. Strojwas, “Impact of interconnect variations on the clock skew of a gigahertz microprocessor”, Proceedings of the Design Automation Conference, June 2000.

Electromagnetic Parasitic Extraction via a Multipole Method with Hierarchical Refinement

M. Beattie and L. Pileggi, “Electromagnetic Parasitic Extraction via a Multipole Method with Hierarchical Refinement”, Proceedings of the International Conference on Computer-Aided Design, November 1999.

Practical Considerations for Passive Reduction of RLC Circuits

A. Odabasioglu, M. Celik & L. T. Pileggi, “Practical Considerations for Passive Reduction of RLC Circuits”, Proceedings of the International Conference on Computer- Aided Design, November 1999.

Efficient and Accurate Delay Metrics for RC Interconnect

A. Odabasioglu, M. Celik & L. T. Pileggi, “Efficient and Accurate Delay Metrics for RC Interconnect”, PATMOS: International Workshop on Power and Timing Modeling, Optimization and Simulation, October 1999.

Model Order-Reduction of RC(L) Interconnect including Variational Analysis

Y. Liu, L. Pileggi and A.J. Strojwas, “Model Order-Reduction of RC(L) Interconnect including Variational Analysis”, Proceedings of the Design Automation Conference (Best Paper Award Nomination), June 1999.

IC Analyses Including Extracted Inductance Models

M. Beattie and L. Pileggi, “IC Analyses Including Extracted Inductance Models”, Proceedings of the Design Automation Conference, Invited Paper, June 1999.

Achieving Timing Closure for Giga-Scale IC Designs

L. Pileggi, “Achieving Timing Closure for Giga-Scale IC Designs”, 1999 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Invited Paper, March 1999.

S2P: Stable 2-Pole Model for RC Interconnect Delay Analysis

E. Acar, A. Odabasioglu, M. Celik and L. Pileggi, “S2P: Stable 2-Pole Model for RC Interconnect Delay Analysis”, Proceedings of the 9th Great Lakes Symposium on VLSI, March 1999.