On the Efficacy of Simplified 2D On-Chip Inductance Models
T. Lin, M. Beattie and L. Pileggi, “On the Efficacy of Simplified 2D On-Chip Inductance Models”, ACM/IEEE Design Automation Conference, June 2002.
Modeling and Analysis of Regular Symmetrically Structured Power/Ground Distribution Networks
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpH. Zheng and L. Pileggi, “Modeling and Analysis of Regular Symmetrically Structured Power/Ground Distribution Networks”, ACM/IEEE Design Automation Conference, June 2002.
Understanding and Addressing the Impact of Wiring Congestion During Technology Mapping
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpD. Pandini, L. Pileggi and A. Strojwas, “Understanding and Addressing the Impact of Wiring Congestion During Technology Mapping”, Int’l Symposium on Physical Design (ISPD), April 2002.
A Linear-Centric Modeling Approach to Harmonic Balance Analysis
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpP. Li and L. Pileggi, “A Linear-Centric Modeling Approach to Harmonic Balance Analysis”, Design and Test in Europe Conference (DATE), March 2002.
On-Chip Inductance Models:3D or not 3D?
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpT. Lin, M. Beattie and L. Pileggi, “On-Chip Inductance Models:3D or not 3D?”, Design and Test in Europe Conference (DATE), March 2002.
A Linear-Centric Simulation Framework for Parametric Fluctuations
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpE. Acar, L. Pileggi and S. Nassif, “A Linear-Centric Simulation Framework for Parametric Fluctuations”, Design and Test in Europe Conference (DATE), March 2002.
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpH. Zhang, B. Krauter, M. Beattie and L. Pileggi, “Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses”, Design and Test in Europe Conference (DATE), March 2002.
Time-Domain Simulation of Variational Interconnect Models
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpE. Acar, S. Nassif and L. Pileggi, “Time-Domain Simulation of Variational Interconnect Models”, Int’l Symposium on Quality in Electronic Design, March 2002.
Congestion-Aware Logic Synthesis
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpD. Pandini, L. Pileggi and A. Strojwas, “Congestion-Aware Logic Synthesis”, Design and Test in Europe Conference (DATE), March 2002.
Min/Max On-Chip Inductance Models and Delay Metrics
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpY-C. Lu, M. Celik, T. Young, and L. Pileggi, “Min/Max On-Chip Inductance Models and Delay Metrics”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
Contact
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774