Design Methodology of Regular Logic Bricks for Robust Integrated Circuits

K.Y. Tong, V. Rovner, L. Pileggi and V. Kheterpal, “Design Methodology of Regular Logic Bricks for Robust Integrated Circuits”, Int’l Conference on Computer Design, October 2006.

Active On-Die Suppression of Power Supply Noise

G. Keskin, X. Li and L. Pileggi, “Active On-Die Suppression of Power Supply Noise”, Int’l Custom Integrated Circuits Conference, Sept. 2006.

A Metric-Embedding Inspired Approach to Timing-driven FPGA Placement

P. Gopalakrishnan, X. Li and L. Pileggi, “A Metric-Embedding Inspired Approach to Timing-driven FPGA Placement”, Design Automation Conference, June 2006.

Projection-Based Statistical Analysis of Full-Chip Leakage Power with Non-Log-Normal Distributions

X. Li, J. Le and L. Pileggi, “Projection-Based Statistical Analysis of Full-Chip Leakage Power with Non-Log-Normal Distributions”, Design Automation Conference, June 2006.

Regular Fabrics for Nano-Scaled CMOS Technologies

L. Pileggi and A.J. Strojwas, “Regular Fabrics for Nano-Scaled CMOS Technologies”, International Solid State Circuits Conference (invited presentation), February 2006.

Maximization of layout printability/manufacturability by extreme layout regularity

T. Jhaveri, L. Pileggi, V. Rovner, A.J. Strojwas, “Maximization of layout printability/manufacturability by extreme layout regularity”, SPIE 31st International Symposium on Microlithography Symposium (invited presentation), February 2006.

Projection-Based Performance Modeling for Inter/Intra-Die Variations

X. Li, J. Le, L. Pileggi and A.J. Strojwas, “Projection-Based Performance Modeling for Inter/Intra-Die Variations”, Proceedings of the International Conference on Computer-Aided Design, November 2005.

Defining Statistical Sensitivity for Timing Optimization of Logic Circuits with Large-Scale Process and Environmental Variations

X. Li, J. Le, M. Celik and L. Pileggi, “Defining Statistical Sensitivity for Timing Optimization of Logic Circuits with Large-Scale Process and Environmental Variations”, Proceedings of the International Conference on Computer-Aided Design, November 2005.

Parameterized Interconnect Order Reduction with Explicit-and-Implicit Multi-Parameter Moment Matching for Inter/Intra-Die Variations

X. Li, P. Li and L. Pileggi, “Parameterized Interconnect Order Reduction with Explicit-and-Implicit Multi-Parameter Moment Matching for Inter/Intra-Die Variations”, Proceedings of the International Conference on Computer-Aided Design, November 2005.

Performance-Centering Optimization for System-Level Analog Design Exploration

X. Li, J. Wang, W. Chiang and L. Pileggi, “Performance-Centering Optimization for System-Level Analog Design Exploration”, Proceedings of the International Conference on Computer-Aided Design, November 2005.