A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS

J. Proesel and L. Pileggi, ‘A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS’, Int’l Custom Integrated Circuits Conference, Sept. 2008.

Variation-Tolerant SRAM Sense-Amplifier Timing Using Configurable Replica Bitlines

U. Arslan, M. McCartney, M. Bhargava, X. Li, K. Mai and L. Pileggi, “Variation-Tolerant SRAM Sense-Amplifier Timing Using Configurable Replica Bitlines”, Int’l Custom Integrated Circuits Conference, Sept. 2008.

Mismatch Analysis and Statistical Design at 65 nm and Below

L. Pileggi, G. Keskin, X. Li, K. Mai and J. Proesel, “Mismatch Analysis and Statistical Design at 65 nm and Below”, Invited Paper, Int’l Custom Integrated Circuits Conference, Sept. 2008.

Variation-Tolerant SRAM Sense-Amp Timing using Configurable Replica Bitlines

U. Arslan, M. McCartney, M. Bhargava, L. Pileggi and K. Mai, “Variation-Tolerant SRAM Sense-Amp Timing using Configurable Replica Bitlines”, Proceedings of the SRC Techcon Conference, September 2008.

A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS

J. Proesel and L. Pileggi, “A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS”, Proceedings of the SRC Techcon Conference, September 2008.

Process Variation Effects on Input Offset Voltage of CMOS SRAM Sense Amplifiers

G. Keskin, L. Pileggi, X. Li and K. Mai, “Process Variation Effects on Input Offset Voltage of CMOS SRAM Sense Amplifiers”, Proceedings of the SRC Techcon Conference, September 2008.

Thermal Analyses of Confined Cell Design for Phase Change Random Access Memory (PCRAM)

E. Small, S.M. Sadeghipour, L. Pileggi, M. Asheghi, “Thermal Analyses of Confined Cell Design for Phase Change Random Access Memory (PCRAM)”, ITherm, May 2008.

Enabling Technology Scaling with ‘In Production’ Lithography Processes

T. Jhaveri, A.J. Strojwas, L. Pileggi, V. Rovner, “Enabling Technology Scaling with ‘In Production’ Lithography Processes”, SPIE Advanced Lithography Conference, February 2008.

Automated Testability Enhancements for Logic Brick Libraries

J. Brown, B. Taylor, R. D. Blanton, and L. Pileggi, “Automated Testability Enhancements for Logic Brick Libraries”, Proceedings of Design and Test Europe, March 2008.

Exact Methods for Physical Design of Regular Logic Bricks

B. Taylor and L. Pileggi, “Exact Methods for Physical Design of Regular Logic Bricks”, Proceedings of the SRC Techcon Conference, October 2007.