Efficient and Secure Intellectual Property (IP) Design with Split Fabrication

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K. Vaidyanathan, R. Liu, E. Sumbul, Q. Zhu, F. Franchetti, L. Pileggi, “Efficient and Secure Intellectual Property (IP) Design with Split Fabrication”, Hardware-Oriented Security and Trust, May 2014.

Building Trusted ICs using Split Fabrication

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K. Vaidyanathan, B. P. Das, E. Sumbul, R. Liu, L. Pileggi, “Building Trusted ICs using Split Fabrication”, Hardware-Oriented Security and Trust, May 2014.

Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack

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K. Vaidyanathan, B. Prasad Das, L. Pileggi, “Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack”, IEEE/ACM Design Automation Conference, June 2014.

Fabrication Challenges in Developing All-Metal Magnetic Logic Circuits

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M. T. Moneck, V. Sokalski, D. M. Bromberg, J. Wu, Z. Dai, L. Pileggi, J.-G. Zhu, “Fabrication Challenges in Developing All-Metal Magnetic Logic Circuits”, 2014 International Magnetics Conference.

mLogic: All Spin Logic Device and Circuits for Future Electronics

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J.-G. Zhu, D. Bromberg, V. Sokalski, M.T. Moneck, J. Wu, Z. Dai, L. Pileggi, “mLogic: All Spin Logic Device and Circuits for Future Electronics”, IEEE Transactions on Magnetics, INTERMAG 2014.

A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI

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V. H-C. Chen and L. Pileggi, “A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI”, International Solid State Circuits Conference (ISSCC), February 2014.

Toward Efficient Programming of Reconfigurable Radio Frequency (RF) Receivers

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J. Tao, Y.-C. Wang, M. Jun, X. Li, R. Negi, T. Mukherjee, L. Pileggi, “Toward Efficient Programming of Reconfigurable Radio Frequency (RF) Receivers”, 19th Asia and South Pacific Design Automation Conference (ASP-DAC), January 2014.

A 3D-Stacked Logic-in-Memory Accelerator for Application-Specific Data Intensive Computing

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Qiuling Zhu, Berkin Akin, H. Ekin Sumbul, James C. Hoe, Larry Pileggi, Franz Franchetti, “A 3D-Stacked Logic-in-Memory Accelerator for Application-Specific Data Intensive Computing”, IEEE International 3D Systems Integration Conference, October 2013.

Indirect Performance Sensing for On-Chip Analog Self-Healing via Bayesian Model Fusion

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S. Sun, F. Wang, S. Yaldiz, X. Li, L. Pileggi, A. Natarajan, M. Ferriss, J. Plouchart, B. Sadhu, B. Parker, A. Valdes-Garcia, M. Sanduleanu, J. Tierno, D. Friedman, “Indirect Performance Sensing for On-Chip Analog Self-Healing via Bayesian Model Fusion”, Int’l Custom Integrated Circuits Conference, September 2013.

A Logic-in-Memory Accelerated 3D-DRAM for Sparse Matrix-Matrix Multiplication

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Qiuling Zhu, Tobias Graf, H. Ekin Sumbul, Larry Pileggi, Franz Franchetti, “A Logic-in-Memory Accelerated 3D-DRAM for Sparse Matrix-Matrix Multiplication”, Seventeenth Annual High Performance Embedded Computing (HPEC) Workshop at MIT Lincoln Laboratory (Best Paper Award), September 2013.