E. Sumbul, A. Patterson, G. Fedder, F. Franchetti, G. Piazza and L. Pileggi, “Trusted Split-Fabrication System-on-Chip Design Technology and Methodology”, (Invited Paper) GOMACTech Technical Program, March 2013.
K. Vaidyanathan, L. Liebmann and L. Pileggi, “Rethinking ASIC design with next-generation lithography and process integration”, SPIE Advanced Lithography Conference, February 2013.
V. Sokalski, D.M. Bromberg, D. Morris, M.T. Moneck, E. Yang, L. Pileggi, J-G. Zhu, “Naturally Oxidized FeCo as a Magnetic Coupling Layer for Electrically Isolated Read/Write Paths in mLogic”, 12th Joint MMM/Intermag Conference, January 2013.
D. Bromberg, D. Morris, L. Pileggi and J. Zhu, “All-Magnetic, Nonvolatile, Addressable Chainlink Memory”, 12th Joint MMM/Intermag Conference, January 2013.
Q. Zhu, L. Pileggi and F. Franchetti, Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography, Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October 2012.
J.-O. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakani, S. Yaldiz, L. Pileggi, R. Harjani, S. Reynolds, J. A. Tierno, D. Friedman, “A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS”, Int’l Custom Integrated Circuits Conference, Sept. 2012.
Q. Zhu, L. Pileggi and F. Franchetti, “Smart Memory Synthesis for Energy-Efficient Computed Tomography Reconstruction”, Proceedings of the SRC Techcon Conference, September 2012.
Q. Zhu, K. Vaidyanathan, O. Shacham, M. Horowitz, L. Pileggi and F. Franchetti, “Design Automation Framework for Application-Specific Logic-in-Memory Blocks”, IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2012.
B. Sadhu, M.A. Ferriss, J-O. Plouchart, A.S. Natarajan, A.V. Rylyakov, A. Valdes-Garcia, B.D. Parker, S. Reynolds, A. Babakhani, S. Yaldiz, L. Pileggi, R. Harjani, J. Tierno and D. Friedman, “A 21.8-27.5GHz PLL in 32nm SOI Using Gm Linearization to Achieve -130dBc/Hz Phase Noise at 10MHz Offset from a 22GHz Carrier”, 2012 Radio Frequency Integrated Circuits Symposium, June 2012.
D. Morris, D. Bromberg, J. Zhu and L. Pileggi, “Magnetic Logic Circuits with Minimal Connections to CMOS”, IEEE CAS-FEST, 2012.
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774