AWE Macromodels for Incorporation in a Circuit Simulator
S.Y. Kim, N. Gopal and L.T. Pillage, “AWE Macromodels for Incorporation in a Circuit Simulator”, Proceedings IEEE International Conference on Computer-Aided Design, November 1992.
Author Archive for: awp
Entries by awp
ETA: Electrical-Level Timing Analysis
R. Brashear, D. Holberg, M.R. Mercer and L.T. Pillage, “ETA: Electrical-Level Timing Analysis”, Proceedings IEEE International Conference on Computer-Aided Design, November 1992.
On the Stability of Moment Matching Approximations in Asymptotic Waveform Evaluation
D. F. Anastasakis, N. Gopal, S.Y. Kim and L.T. Pillage, “On the Stability of Moment Matching Approximations in Asymptotic Waveform Evaluation”, Proceedings Design Automation Conference, June 1992.
Non-Uniform Models for Transmission Line Analysis
N. Gopal, E. Tuncer, D. Neikirk and L.T. Pillage, “Non-Uniform Models for Transmission Line Analysis”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, April, 1992.
Effects of RC-Interconnect in a Hierarchical Timing Analyzer
C. Ratzlaff, S. Pullela and L.T. Pillage, “Effects of RC-Interconnect in a Hierarchical Timing Analyzer”, Proceedings Custom Integrated Circuits Conference, May 1992.
Evaluating RC Interconnect Using Moment Methods
N. Gopal, D. Neikirk and L.T. Pillage, “Evaluating RC Interconnect Using Moment Methods” Proceedings IEEE International Conference on Computer-Aided Design, November 1991.
Constrained Approximation of Dominant Time Constants in RC Circuit Delay Models
N. Gopal, C. Ratzlaff, L.T. Pillage, “Constrained Approximation of Dominant Time Constants in RC Circuit Delay Models”, Proceedings of the International Mathematics and Computation Symposium, (Invited Paper), July 1991.
RICE: Rapid Interconnect Circuit Evaluator
C. Ratzlaff, N. Gopal, L.T. Pillage, “RICE: Rapid Interconnect Circuit Evaluator”, Proceedings Design Automation Conference, (Best Paper Award Nomination), June 1991.
Calculation and Application of Time-Domain Sensitivities in Asymptotic Waveform Evaluation
A. Balivada, D. Holberg and L.T. Pillage, “Calculation and Application of Time-Domain Sensitivities in Asymptotic Waveform Evaluation”, Proceedings Custom Integrated Circuits Conference, May 1991.
DC Parametrized Piecewise Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation
D. Holberg, S. Dutta and L.T. Pillage, “DC Parametrized Piecewise Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation”, Proceedings IEEE International Conference on Computer-Aided Design, November 1990.
