S. Pullela, N. Menezes and L.T. Pillage, “Skew and Delay Optimization for Reliable Buffered Clock Trees”, Proceedings of the 1993 International Conference on Computer-Aided Design, Nov. 1993.
S. Y. Kim, E. Tuncer, R. Gupta, B. Krauter, T.L. Savarino, D. P. Neikirk and L. T. Pillage, “An Efficient Methodology for Extraction and Simulation of Transmission Lines for Application Specific Electronic Modules”, Proceedings of the 1993 International Conference on Computer-Aided Design, Nov. 1993.
E. Tuncer, S.Y. Kim, L.T. Pillage and D. Neikirk, A New, “Efficient Circuit Model for Microstrip Lines Including Both Current Crowding and Skin Depth Effects”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, October 1993.
S. Pullela, N. Menezes and L.T. Pillage, “Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization”, Proceedings Design Automation Conference, June 1993.
D.C. Yuan, L.T. Pillage, and J.T. Rahmeh, “Evaluation by Parts of Mixed-Level dc- Connected Components in Logic Simulation”, Proceedings Design Automation Conference, June 1993.
S.Y. Kim, N. Gopal and L.T. Pillage, “Finite-Pole Macromodels of Transmission Lines for Circuit Simulation”, Proceedings Custom Integrated Circuits Conference, May 1993.
V. Raghavan, R.A. Rohrer, L.T. Pillage, J.Y. Lee, J.E. Braken, M.M. Alaybeyi, AWE-Inspired, “Proceedings Custom Integrated Circuits Conference”, (Invited Tutorial Paper), May 1993.
N. Menezes, S. Pullela, A. Balivada and L.T. Pillage, “Skew Reduction in Clock Trees Using Wire Width Optimization”, Proceedings Custom Integrated Circuits Conference, May 1993.
Lawrence T. Pillage, “An Early Introduction to Circuit Simulation Techniques, IEEE Transactions on Education”, February 1993.
M. Becker, D. Beer, M.J. Gonzalez, C.M. Maziar, L.T. Pillage, M.D. Shermis, T.J. Wagner, G.L. Wise, “Introduction to Electrical and Computer Engineering”, Proceedings of the 1992 American Society on Engineering Education Annual Conference, November 1992
