A Sparse Image Method for BEM Capacitance Extraction
Byron Krauter, Yu Xia, Aykut Dengi, Lawrence T. Pileggi, “A Sparse Image Method for BEM Capacitance Extraction”, Proceedings of the Design Automation Conference, 1996.
Author Archive for: awp
Entries by awp
An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response
Bogdan Tutuianu and Lawrence Pileggi, “An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response”, Proceedings of the Design Automation Conference , 1996.
Performance Computation for Pre-characterized CMOS Gates with RC Loads
F. Dartu, N. Menezes and L.T. Pileggi, “Performance Computation for Pre-characterized CMOS Gates with RC Loads”, IEEE Transactions on Computer-Aided Design, pp. 544-553, May 1996.
Domain Characterization of Transmission Line Models and Analyses
Rohini Gupta, Seok-Yoon Kim and Lawrence Pileggi, “Domain Characterization of Transmission Line Models and Analyses”, IEEE Transactions on Computer-Aided Design, pp. 184-193, February 1996.
On Moment Based Metrics for Optimal Termination of Transmission Line Interconnects
R. Gupta, B. Krauter and L. Pileggi, “On Moment Based Metrics for Optimal Termination of Transmission Line Interconnects”, Proceedings of the 9th International Conference on VLSI Design, January 1996.
Two Optimizations to Accelerated Method-of-Moments Algorithms for Signal Integrity Analysis of Complicated 3-D Packages
M. Kamon, B. Krauter, J. Phillips, L. Pileggi, and J. White, “Two Optimizations to Accelerated Method-of-Moments Algorithms for Signal Integrity Analysis of Complicated 3-D Packages”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, November 1995.
The Elmore Delay as a Bound for RC-Trees with Generalized Input Signals
R. Gupta, B. Krauter, B. Tutuianu, J. Willis and L. Pileggi, “The Elmore Delay as a Bound for RC-Trees with Generalized Input Signals”, Proceedings of the Design Automation Conference, 1995.
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization
N. Menezes, S. Pullela and L. Pileggi, “Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization”, Proceedings of the Design Automation Conference, 1995.
Transmission Line Synthesis
B. Krauter, R. Gupta, J. Willis and L. Pileggi, “Transmission Line Synthesis”, Proceedings of the Design Automation Conference , 1995.
Timing Analysis Models for Gates and Cells with Bipolar Transistor Output Stages
I. Tesu and L. Pileggi, “Timing Analysis Models for Gates and Cells with Bipolar Transistor Output Stages”, Proceedings of the IEEE ASIC Conference, 1995.
