Rohini Gupta, John Willis and L.T. Pileggi, “Analytic Termination Metrics for Pin-to- Pin Lossy Transmission Lines with Nonlinear Drivers”, IEEE Transactions on VLSI Systems, Vol. 6, No. 3, pp. 457-463, September 1998.
A. Odabasioglu, M. Celik and L. T. Pileggi, “PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm”, IEEE Transactions on Computer-Aided Design (1999 IEEE Best Paper Award), Vol. 17, No. 8, pp. 645-654, August 1998.
R. Kay and L. Pileggi, EWA: “Efficient Wire Sizing Algorithm”, IEEE Transactions on Computer-Aided Design, January, 1998.
Rony Kay and Lawrence Pileggi, “PRIMO: Probability Interpretation of Moments for Delay Calculation”, Proceedings of the Design Automation Conference, June 1998.
Frank Liu, Lawrence Pileggi and Andrzej Strojwas, ftd: “An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models”, Proceedings of the Design Automation Conference, June 1998.
Florin Dartu and Lawrence Pileggi, “TETA: Transistor-Level Engine for Timing Analysis”, Proceedings of the Design Automation Conference, June 1998.
L. Pileggi, “Timing Metrics for Physical Design of Deep Submicron Technologies”, Invited paper, International Symposium on Physical Design, April 1998.
Zhijiang (John) He and Lawrence T. Pileggi, “A Simple Algorithm for Calculating Frequency-Dependent Inductance Bounds”, Proceedings of the Custom Integrated Circuits Conference, May 1998.
M. Celik and L. T. Pileggi, “Simulation of Lossy Multiconductor Transmission Lines Using Backward Euler”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 45, No. 3, pp. 238-243, March 1998.
N. Menezes, R. Baldick and L.T. Pileggi, “A Sequential Quadratic Programming Approach to Concurrent Gate and Interconnect Sizing”, IEEE Transactions on Computer- Aided Design, August 1997.
