Min/Max On-Chip Inductance Models and Delay Metrics
Y-C. Lu, M. Celik, T. Young, and L. Pileggi, “Min/Max On-Chip Inductance Models and Delay Metrics”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
Author Archive for: awp
Entries by awp
RC(L)Interconnect Sizing With Second Order Considerations via Posynomial Programming
T. Lin and L. Pileggi, “RC(L)Interconnect Sizing With Second Order Considerations via Posynomial Programming”, Int’l Symposium on Physical Design (ISPD), April 2001.
Overcoming Wireload Model Uncertainty During Physical Design
P. Gopalakrishnan, A. Odabasioglu, L. Pileggi and S. Raje, “Overcoming Wireload Model Uncertainty During Physical Design”, Int’l Symposium on Physical Design (ISPD), April 2001.
ftd: Frequency to Time Domain Conversion for Reduced Order Interconnect Circuits
Y. Liu, L. T. Pileggi and A.J. Strojwas, “ftd: Frequency to Time Domain Conversion for Reduced Order Interconnect Circuits”, IEEE Transactions on Circuits and Systems, April 2001.
Efficient Inductance Extraction via Windowing
M. Beattie and L. Pileggi, “Efficient Inductance Extraction via Windowing”, Design and Test in Europe Conference (DATE), March 2001.
Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations
E. Acar, S. Nassif and L. Pileggi, Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations, Int’l Symposium on Quality in Electronic Design, March 2001.
Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI
R.E. Bryant, K.T. Cheng, A.B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. Rabaey and A. Sangiovanni-Vincentelli, “Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI”, Proceedings of the IEEE, Special Issue on the Limits of Semiconductor Technology, pp. 341-366, March 2001.
Equipotential Shells for Efficient Inductance Extraction
M. Beattie, B. Krauter, L. Alatan and L. Pileggi, “Equipotential Shells for Efficient Inductance Extraction”, IEEE Transactions on Computer-Aided Design, Vol. 20, No. 1, January 2001.
Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations
E. Acar, S. Nassif and L. Pileggi, “Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations”, ACM/IEEE Workshop on Timing in the Specification and Synthesis of Digital Systems, December 2000.
Hierarchical Interconnect Circuit Models
M. Beattie, S. Gupta, L. Pileggi, “Hierarchical Interconnect Circuit Models”, Proceedings of the International Conference on Computer-Aided Design, November 2000.
