All-Magnetic, Nonvolatile, Addressable Chainlink Memory
D. Bromberg, D. Morris, L. Pileggi and J. Zhu, “All-Magnetic, Nonvolatile, Addressable Chainlink Memory”, 12th Joint MMM/Intermag Conference, January 2013.
Author Archive for: awp
Entries by awp
Naturally Oxidized FeCo as a Magnetic Coupling Layer for Electrically Isolated Read/Write Paths in mLogic
V. Sokalski, D.M. Bromberg, D. Morris, M.T. Moneck, E. Yang, L. Pileggi, J-G. Zhu, “Naturally Oxidized FeCo as a Magnetic Coupling Layer for Electrically Isolated Read/Write Paths in mLogic”, 12th Joint MMM/Intermag Conference, January 2013.
Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation
Q. Zhu, C. Berger, E. Turner, L. Pileggi and F. Franchetti, “Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation”, Journal of Signal Processing Systems, 2012.
Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography
Q. Zhu, L. Pileggi and F. Franchetti, Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography, Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October 2012.
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
J.-O. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakani, S. Yaldiz, L. Pileggi, R. Harjani, S. Reynolds, J. A. Tierno, D. Friedman, “A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS”, Int’l Custom Integrated Circuits Conference, Sept. 2012.
Smart Memory Synthesis for Energy-Efficient Computed Tomography Reconstruction
Q. Zhu, L. Pileggi and F. Franchetti, “Smart Memory Synthesis for Energy-Efficient Computed Tomography Reconstruction”, Proceedings of the SRC Techcon Conference, September 2012.
Design Automation Framework for Application-Specific Logic-in-Memory Blocks
Q. Zhu, K. Vaidyanathan, O. Shacham, M. Horowitz, L. Pileggi and F. Franchetti, “Design Automation Framework for Application-Specific Logic-in-Memory Blocks”, IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2012.
A 21.8-27.5GHz PLL in 32nm SOI Using Gm Linearization to Achieve -130dBc/Hz Phase Noise at 10MHz Offset from a 22GHz Carrier
B. Sadhu, M.A. Ferriss, J-O. Plouchart, A.S. Natarajan, A.V. Rylyakov, A. Valdes-Garcia, B.D. Parker, S. Reynolds, A. Babakhani, S. Yaldiz, L. Pileggi, R. Harjani, J. Tierno and D. Friedman, “A 21.8-27.5GHz PLL in 32nm SOI Using Gm Linearization to Achieve -130dBc/Hz Phase Noise at 10MHz Offset from a 22GHz Carrier”, 2012 Radio Frequency Integrated Circuits […]
Magnetic Logic Circuits with Minimal Connections to CMOS
D. Morris, D. Bromberg, J. Zhu and L. Pileggi, “Magnetic Logic Circuits with Minimal Connections to CMOS”, IEEE CAS-FEST, 2012.
mLogic: Ultra-Low Voltage Non-Volatile Logic Circuits Using STT-MTJ Devices
D. Morris, D. Bromberg, J. Zhu and L. Pileggi, “mLogic: Ultra-Low Voltage Non-Volatile Logic Circuits Using STT-MTJ Devices”, IEEE/ACM Design Automation Conference (DAC), 2012.
