Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations
Xin Li, Jiayong Le, Mustafa Celik and Lawrence Pileggi, “Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 6, pp. 1041-1054, June 2008.
