Efficient Inductance Extraction via Windowing

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M. Beattie and L. Pileggi, “Efficient Inductance Extraction via Windowing”, Design and Test in Europe Conference (DATE), March 2001.

Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations

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E. Acar, S. Nassif and L. Pileggi, Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations, Int’l Symposium on Quality in Electronic Design, March 2001.

Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI

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R.E. Bryant, K.T. Cheng, A.B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. Rabaey and A. Sangiovanni-Vincentelli, “Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI”, Proceedings of the IEEE, Special Issue on the Limits of Semiconductor Technology, pp. 341-366, March 2001.