S2P: Stable 2-Pole Model for RC Interconnect Delay Analysis
E. Acar, A. Odabasioglu, M. Celik and L. Pileggi, “S2P: Stable 2-Pole Model for RC Interconnect Delay Analysis”, Proceedings of the 9th Great Lakes Symposium on VLSI, March 1999.
Archive for month: March, 1999
Achieving Timing Closure for Giga-Scale IC Designs
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpL. Pileggi, “Achieving Timing Closure for Giga-Scale IC Designs”, 1999 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Invited Paper, March 1999.
Bounds for BEM Capacitance Extraction
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpM. Beattie and L. T. Pileggi, “Bounds for BEM Capacitance Extraction”, IEEE Transactions on Computer-Aided Design, Vol. 18, No. 3, pp. 311-321, March 1999.
Metrics and Bounds for Phase Delay and Signal Attenuation in RCL Clock Trees
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpM. Celik and L. T. Pileggi, “Metrics and Bounds for Phase Delay and Signal Attenuation in RCL Clock Trees”, IEEE Transactions on Computer-Aided Design, Vol. 18, No. 3, pp. 293-300, March 1999.
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