Documents
The following documents are available in postscript and/or .pdf formats:
Abstract: The SIA Roadmap, derived from the Moore's Law, promotes continuation of the decrease in minimum feature size and wafer size increase as bases for the Semiconductor Industry successful future. Such a vision has a number of important implications. One of them is an increase in the die manufacturing cost. The objective of this talk is to demonstrate, by using data derived directly from 1997 SIA Roadmap, that die cost increase is on one hand unavoidable, and on the other hand unacceptable. The following discussion will also suggest a few alternatives to the 1997 SIA Roadmap which can relax for a while a "cost contradiction" built-into the SIA Roadmap.
This talk was presented in 1998 in several industrial seminars.
• W. Maly, "High Levels of IC Manufacturability: One of the Necessary Prerequisites Of the 1997 SIA Roadmap Vision".
Abstract: The SIA Roadmaps promote aggressive decrease in minimum feature size, which is likely to result in a severe contradiction between acceptable die cost and achievable manufacturing cost. In this paper such a contradiction is discussed in detail along with its likely negative consequences. Efficient Design for Manufacturability is indicated as one of a few remedies, which may help the IC industry in relaxing the implications of the cost contradiction, generated by the SIA Roadmaps.
This paper is included in Proc. of International Electron Device Meeting (IEDM), San Francisco, December 6-9, 1998, pages 759-762..
• W. Maly, "Moore’s Law and Physical Design".
Abstract: Moore’s Law -- a self-fulfilling prophecy -- has provided important guidance for the IC industry since the beginning of the microelectronics era. In its most detailed reincarnation Moore’s Law took the form of the National Technology Roadmap for Semiconductors (NTRS). The currently observed “renaissance” of physical design -- a domain pronounced dead a couple years ago by some experts -- is a direct consequence of the NTRS mandated direction of IC industry evolution. This talk discusses the newest 1997 NTRS in order to foresee the nature of further progress in physical design of ICs.
This talk was presented at 1998 International Symposium on Physical Design, Monterey, April 6-8,1998..
• W. Maly, "Cost-Oriented Analysis of the 1997 NTRS".
Abstract: This document is a summary of the analysis of the 1997 National Technology Roadmap for Semiconductors (NTRS). Discussion is focused on the cost of IC manufacturing. It is shown that the Roadmap’s assumptions lead to unacceptable high die cost at the same time restricting cost of manufacturing to a very low level. This document is concluded with the discussion of possible consequences of such a cost contradiction built-into 1997 NTRS.
• W. Maly," IC Design Test Research Directions Derived from the 1997 SIA Road Vision ".
Abstract: This document discusses the impact of the 1997 Semiconductor Industry Association (SIA) Roadmap on Design and Test (D&T) of Integrated Circuits (ICs). First, the discussion is focused on the cost of IC manufacturing to emphasize the increasing level of difficulty in achieving subsequent milestones of the Roadmap. This increase must be taken into account as a key factor in setting research priorities for the entire semiconductor industry including D&T domain. Second, some of these priorities for the D&T arena are discussed in detail. A list of D&T research tasks which should be initiated now in order to address SIA Roadmap generated needs is also proposed.
• W.Maly," Cost of Silicon Viewed from VLSI Design Perspective ".
Abstract: This paper provides an overview of design/test/CAD silicon cost-related issues. All major factors contributing to the rapid growth of manufacturing costs are explained and a simple cost model is introduced to assess possible impact of cost growth on the VLSI arena.
This paper was published in Proc. of DAC-94, San Diego, June 1994, pp. 135-142.
• W. Maly , H. Jacobs and A. Kersch," Estimation of Wafer Cost for Technology Design ".
Abstract: A simple cost model, capturing relationship between cost of the equipment ownership and the cost of manufacturing wafer, is proposed. This model is constructed in a way allowing for "fair" allocation of the cost of equipment idle time among products fabricated with significantly different technologies, sharing the same fabline. A necessary cost of equipment ownership data base has been built and a number of detailed process flows have been constructed. Finally, cost analysis for three categories of manufacturing scenarios: R&D, ASIC and high volume has been conducted. Results indicate large wafer cost differences between high volume and lower volume manufacturing strategies. These differences also indicate that newer complex processes and manufacturing strategies should be developed with an aid of a cost modeling technique such as one described in this paper.
This paper was published in Proc. of IEDM-93, Washington D.C., Dec. 5-8, 1993, pp. 35.6.1 - 35.6.4.
• W. Maly, D. B.I. Feltham, A. E. Gattiker, M. D. Hobaugh, K. Backus and M. E. Thomas," Multi-Chip Module Smart Substrate Systems ".
Abstract: This paper proposes a Smart Substrate Multi-chip Module system implementation strategy. This strategy enables incremental test of all system components and therefore provides an alternative solution to the "Known Good Die" MCM problem. The presentation is focused on a simple microcontroller emulator - designed and fabricated to study test logic needed as a key component of Smart Substrate methodology.
This paper was published in IEEE Design & Test of Computers, Summer 1994, pp. 64-73.
• P.K.Nag, W.Maly and H.Jacobs," Advanced Forecasting Cost and Yield".
Abstract: This article describes a prototype of a discrete event simulator - Y4 (Yield Forecaster) - capable of simulating defect related yield loss as a function of time, for a multi-product IC manufacturing line. The methodology of estimating yield and cost is based on mimicking the operation and characteristics of a manufacturing line in the time domain. The effect of particles introduced during wafer processing as well as changes in their densities due to process improvements are taken into account. A spectrum of results are presented for a manufacturing scenario to demonstrate the usefulness of the simulator in formulating IC manufacturing strategies.
This paper has been published in Semiconductor International pp. 163 - 170, July 1998.
