PhD student
Electrical and Computer Engineering
Carnegie Mellon University
CIC 4th Floor
Pittsburgh PA 15213

I am pursuing my PhD in Electrical & Computer Engineering. I received my bachelors in Electronics & Communication Engineering from Madras Institute of Technology, India in 2007 and my masters in Electrical & Computer Engineering from Carnegie Mellon in 2012. More about me in my resume.


I work in the broad area of computer architecture with my advisor Prof. Onur Mutlu.

My specific research interests are in main memory management and providing predictable application performance in the presence of shared resources, in both homogeneous and heterogeneous systems.


I enjoyed being a teaching assistant for

Introduction to Computer Architecture,
18-447, Spring 2012 and
Graduate Computer Architecture,
18/15-740, Fall 2010.

I played an active role in different aspects of the courses such as conducting recitations, developing homeworks, exams.


Hui Wang, Canturk Isci, Lavanya Subramanian, Jongmoo Choi, Depei Qian, Onur Mutlu, A-DRM: Architecture-aware Distributed Resource Management of Virtualized Clusters, in Proceedings of the 11th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE), 2015. [ pdf | slides (talk delivered by Hui Wang)]

Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, Onur Mutlu, The Blacklisting Memory Scheduler: Achieving High Performance and Fairness at Low Cost, in Proceedings of the 32nd International Conference on Computer Design (ICCD), 2014. [ pdf | slides ]

Lavanya Subramanian, Vivek Seshadri, Yoongu Kim, Ben Jaiyen, Onur Mutlu, MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems., in Proceedings of the 19th International Symposium on High-Performance Computer Architecture (HPCA), 2013. [ pdf | slides ]

Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu, Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture, in proceedings of the 19th International Symposium on High-Performance Computer Architecture (HPCA), 2013. [ pdf | slides (talk delivered by Donghyuk Lee) ]

Rachata Ausavarungnirun, Kevin Chang, Lavanya Subramanian, Gabriel Loh, Onur Mutlu, Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems, in proceedings of the 39th International Symposium on Computer Architecture (ISCA), 2012. [ pdf | slides (talk delivered by Rachata Ausavarungnirun) ]

Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut Kandemir, Thomas Moscibroda, Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning, in proceedings of the 44th International Symposium on Microarchitecture (MICRO), 2011. [ pdf | slides ]

Lavanya Subramanian, Gayatri Singaravelu, Arunachalam Annamalai, Kannan M., Reduced Computation Memory Access Efficient VLSI Implementation of Enhanced Successive Elimination Algorithm for Multimedia Processors, in proceedings of the International Conference on Signal and Image Processing (ICSIP), 2006.

Invited Papers

Onur Mutlu, Justin Meza Lavanya Subramanian, The Main Memory System: Challenges and Opportunities, Communications of the Korean Institute of Information Scientists and Engineers (KIISE), 2015.

Onur Mutlu, Lavanya Subramanian, Research Problems and Opportunities in Memory Systems, To Appear in Supercomputing Frontiers and innovations (Superfri), 2015.

Technical Reports

Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, Onur Mutlu, The Blacklisting Memory Scheduler: Balancing Performance, Fairness and Complexity, SAFARI Technical Report No. 2015-004. March 27, 2015. [pdf]

Hiroyuki Usui, Lavanya Subramanian, Kevin Chang, Onur Mutlu, SQUASH: Simple QoS-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators, SAFARI Technical Report No. 2015-003. March 18, 2015. [pdf]

Kevin Chang, Gabriel H. Loh, Mithuna Thottethodi, Yasuko Eckert, Mike O Connor, Lavanya Subramanian, Onur Mutlu, Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism, SAFARI Technical Report No. 2013-001. April 30, 2013. [pdf]

Outside of Work

I enjoy reading non-fiction and fiction. I am also into Indian classical music and enjoy singing and listening.