Publications & Talks              [ 2009 | 2008 | 2007 | 2005 | 2004 | 2003 and earlier ]     

2009

E. Chung, M. Papamichael, E. Nurvitadhi, J. Hoe, B. Falsafi, and K. Mai, “ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs,” ACM Transactions on Reconfigurable Technology and Systems, 2009, to appear.

J. Kim, M. McCartney, K. Mai, and B. Falsafi , “Modeling SRAM Failure Rates to Enable Fast, Dense, Low-Power Caches,” IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE-5), March 2009.

2008

U. Arslan, M. McCartney, M. Bhargava, X. Li, K. Mai, L. Pileggi, “Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines,” IEEE Custom Integrated Circuits Conference, Sept. 2008.

L. Pileggi, G. Keskin, X. Li, K. Mai, J. Proesel, “Mismatch analysis and statistical design at 65 nm and below,” IEEE Custom Integrated Circuits Conference, Sept. 2008.

E. Mendez and K. Mai, “A High-Performance, Low-Overhead, Power-Analysis-Resistant, Single-Rail Logic Style,” Proceedings of IEEE International Workshop Hardware-Oriented Security and Trust, June 9, 2008.

E. Chung, E. Nurvitadhi, J. Hoe, B. Falsafi, and K. Mai, ”A Complexity-Effective Architecture for Accelerating Full-System Multiprocessor Simulations Using FPGAs,” Proceedings of ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, February 24-26, 2008.

B. Calhoun, X. Li, K. Mai, L. Pileggi, R. Rutenbar, K. Shepard, “Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS” Proceedings of the IEEE, Feb. 2008.

2007

J. Kim, N. Hardavellas, K. Mai, B. Falsafi, J. Hoe, “Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding,” IEEE/ACM International Symposium on Microarchitecture, December 2007.

B. Gold, M. Ferdman, B. Falsafi, K. Mai, “Mitigating Multi-bit Soft Errors in L1 Caches Using Last Store Prediction,” Workshop on Architectural Support for Gigascale Integration, June 2007.

S. Chellappa, F. Mesmay, J. Smolens, B. Falsafi, J. Hoe, K. Mai, “Fingerprinting Across On-Chip Memory Interconnects,” IEEE Workshop on Silicon Errors in Logic - System Effects, April 2007.

J. Smolens, B. Gold, J. Hoe, B. Falsafi, K. Mai, “Detecting Emerging Wearout Faults,” Workshop on Silicon Errors in Logic - System Effects April 2007.

E. Chung, E. Nurvitadhi, J. Hoe, B. Falsafi, K. Mai, “ProtoFlex: FPGA-accelerated Hybrid Functional Simulator,” IEEE International Parallel and Distributed Processing Symposium, March 2007.

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2005

K. Mai, R. Ho, E. Alon, D. Liu, Y. Kim, D. Patil, M. Horowitz, “Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18µm CMOS,” IEEE Journal of Solid-State Circuits, January 2005.

2004

H. Lee, C. Yue, S. Palermo, K. Mai, M. Horowitz, “Burst Mode Packet Receiver using a Second Order DLL,” Digest of Technical Papers, Symposium on VLSI Circuits, June 2004.

K. Mai, R. Ho, E. Alon, D. Liu, Y. Kim, D. Patil, M. Horowitz, “Architecture and Circuit Techniques for a Reconfigurable Memory Block,” Digest of Technical Papers, IEEE International Solid-State Circuits Conference, February 2004.

R. Ho, K. Mai, M. Horowitz, “Efficient On-Chip Global Interconnects,” Digest of Technical Papers, Symposium on VLSI Circuits, June 2003.

2003 and earlier

R. Ho, K. Mai, M. Horowitz, “ManagingWire Scaling: A Circuit Perspective,” Proceedings of the IEEE International Interconnect Technology Conference, June 2003.

R. Ho, K. Mai, M. Horowitz, “The Future of Wires,” Proceedings of the IEEE, Vol. 89, Issue 4, April 2001.

K. Mai, T. Paaske, N. Jayasena, R. Ho, W. Dally, M. Horowitz, “Smart Memories: A Modular Reconfigurable Architecture,” Proceedings of the 27th International Symposium on Computer Architecture, June 2000.

R. Ho, K. Mai, H. Kapadia, M. Horowitz, “Interconnect Scaling Implications for CAD,” Digest of Technical Papers, IEEE/ACM International Conference on Computer-Aided Design, November 1999.

K. Mai, T. Mori, B. Amrutur, R. Ho, B. Wilburn, M. Horowitz, I. Fukushi, T. Izawa, S. Mitarai, “Low-Power SRAM Design Using Half-Swing Pulse-Mode Techniques,” IEEE Journal of Solid-State Circuits, Vol. 33, Issue 11, November 1998.

R. Ho, B. Amrutur, K. Mai, B. Wilburn, T. Mori, M. Horowitz, “Applications of On-Chip Samplers for Test and Measurement of Integrated Circuits,” Digest of Technical Papers, Symposium on VLSI Circuits, June 1998.

T. Mori, B. Amrutur, K. Mai, M. Horowitz, I. Fukushi, T. Izawa, S. Mitarai, “A 1V 0.9mW at 100MHz 2k*16b SRAM Utilizing a Half-Swing Pulsed Decoder and Write-Bus Architecture in 0.25µm Dual-Vt CMOS,” Digest of Technical Papers, IEEE International Solid State Circuits Conference, February 1998.

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