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Robust Memory Design using Digital Communications Techniques

We are exploring microarchitectural and circuit-level techniques for increasting the resilience, performance, area, and power of semiconductor memories using techniques from digital communications. These techniques primarily consist of strong multi-bit error correcting codes which we can use to tolerate a number of bit-errors in a memory word without using redundant elements. We are particularly interested in how to implement strong ECC without incurring large area, power, and performance overheads.