18-100 Course Schedule and Lecture Notes, Spring 2015

  • Lecture
    • TR 01:30PM 02:50PM DH 2315


Week Date L# Topic
1 1/13 L1 Introduction, discussion of engineering systems and sub-systems, basic electricity
1/15 L2 Voltage, current, resistance, power, circuit schematic symbols, ground
2 1/20 L3 Power dissipation, Ohm's law, Kirchoff's Voltage and Current Laws, basic circuits
1/22 L4 Series and parallel resistances and combinations, solving circuits using equivalent resistances
3 1/27 L5 Superposition, Thevenin and Norton Equivalents, Source Transformation
1/29 L6 Introduction to capacitors and inductors, impedance, begin 1st order systems
4 2/3 L7 Continue 1st order systems, RC and LR circuits, time and freq. domain
2/5 L8 2nd order systems, LRC circuits, frequency response
5 2/10 L9 Wrap up any remaining LRC circuit items. Review for Exam 1
2/12 L10 Introduction to Operational Amplifiers, open and closed loop gain, op-amp assumptions, inverting and non-inverting amplifier circuits
6 2/17 Exam I
2/19 L11 Buffers, summing and difference circuits, active filters
7 2/24 L12 Introduction to diodes (signal, zener, and LED), basic diode operation, piecewise linear model (PWL) for diodes, rectifiers
2/26 L13 Introduction to transistors, basic transistor operation, piecewise linear model for NPN transistors, common emitter circuits
8 3/3 L14 Introduction to the field effect transistor (FET) and its operating regions. Common drain transistor circuit, FET switches.
3/5 L15 Small signal analysis of transistor circuits, amplifiers
Spring Break
9 3/17 L16 Signals and modulation
3/19 L17 Sampling, analog to digital conversion, quantization, base conversions, binary arithmetic
10 3/24 L18 Wrap up any remaining signal processing items. Review for Exam 2
3/26 L19 Introduction to Computer Systems, begin basic assembly language
11 3/31 Exam II
4/2 L20 Basic assembly language (cont.)
12 4/7 L21 Logic gates, Boolean expressions, DeMorgan's theorems, begin combinational logic circuits
4/9 L22 Combinational logic circuits (cont.), truth tables, digital circuit schematics, two-level circuit representation
13 4/14 L23 Karnaugh maps, adders, multiplexers, de-multiplexers
4/16 No class, Spring Carnival
14 4/21 L24 Feedback in logic circuits, SR flip-flops, D flip-flops, master-slave edge-triggered flip-flops, sequential logic, state diagrams, state transition tables, begin finite state machine design
4/23 L25 Continue finite state machine design, design of counters, output mapping, sequential logic circuits with external inputs
15 4/28 L26 Review for Exam III
4/30 Exam III
5/8 Final Exam, 8:30~11:30, GHC 4401