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| a_short_intro_to_modelsim_verilog_simulator [2020/09/03 22:08] – Added optimization control details shashankov | a_short_intro_to_modelsim_verilog_simulator [2022/09/01 18:08] (current) – [Running ModelSim] edit |
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| ''vlog <<list of verilog files>>'' | ''vlog <<list of verilog files>>'' |
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| This might look like (try [[http://www.ece.cmu.edu/~jhoe/distribution/example.zip |example.zip]]) | This might look like (try [[https://users.ece.cmu.edu/~jhoe/distribution/example.zip |example.zip]]) |
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| ''vlog op.v recip.v top.v'' | ''vlog op.v recip.v top.v'' |
| The simulation will run until it encounters a ''$stop'' or ''$finish'' command in your .v files. If you are using only ''$display'' and ''$print'' for debugging, this is all the ModelSim you need know. In fact, if this is all you do, you can just type | The simulation will run until it encounters a ''$stop'' or ''$finish'' command in your .v files. If you are using only ''$display'' and ''$print'' for debugging, this is all the ModelSim you need know. In fact, if this is all you do, you can just type |
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| ''vsim -c -do "run -all" top'' | ''vsim -c -do "run -all" top'' |
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| | //(Note: in the above, if you cut-and-paste, you need to retype with straight quotation marks.)// |
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| at the Unix command prompt to run vsim in text mode (without X). | at the Unix command prompt to run vsim in text mode (without X). |
| As was hinted earlier, Modelsim performs aggressive optimizations by default. To debug you need to make sure that the optimizer is aware of the level of debug information it needs to retain. There are a couple of ways to go about this: | As was hinted earlier, Modelsim performs aggressive optimizations by default. To debug you need to make sure that the optimizer is aware of the level of debug information it needs to retain. There are a couple of ways to go about this: |
| * **Global Optimization**: Add the option ''-voptargs="+acc"'' to the ''vsim'' command. This enables full visibility into every aspect of the design. The command might look like: ''vsim --voptargs="+acc" <top_level>'' | * **Global Optimization**: Add the option ''-voptargs="+acc"'' to the ''vsim'' command. This enables full visibility into every aspect of the design. The command might look like: ''vsim --voptargs="+acc" <top_level>'' |
| * **File Level Optimization**: This is a more powerful option which lets you control optimization of specific HDL files and hence modules. Add the option ''+acc'' to the ''vlog'' command for the files you want to have view into. For example you wanted to look into a module named top in ''top.v'' you'd use the following command just for that file: ''vlog +acc top.v''. You can compile the rest of the files as usual. | * **File Level Optimization**: This is a more powerful option which lets you control optimization of specific HDL files and hence modules. Add the option ''+acc'' to the ''vlog'' command for the files you want to have view into. For example if you wanted to look into a module named top in ''top.v'' you'd use the following command just for that file: ''vlog +acc top.v''. You can compile the rest of the files as usual. |
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| Here's a full list of possible options other than just using ''+acc'' which can also be obtained by running the command ''vlog -help Debug'' | Here's a full list of possible options other than just using ''+acc'' which can also be obtained by running the command ''vlog -help Debug'' |
