Yoongu

Yoongu Kim


Electrical & Computer Engineering
Carnegie Mellon University

Email: yoongukim at cmu.edu
Office: CIC 4th Floor


BIO

I'm a Ph.D. student in the ECE department at Carnegie Mellon University (since 2008). Previously, I received my B.S. in electrical engineering from Seoul National University.

I'm a recipient of a Ph.D. fellowship from the Korea Foundation for Advanced Studies (KFAS).


RESEARCH

I'm interested in high-performance, energy-efficient, and reliable memory subsystems. I work closely with Prof. Onur Mutlu.


PUBLICATIONS

ISCA '13 An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms
Jamie Liu, Ben Jaiyen, Yoongu Kim, Chris Wilkerson, and Onur Mutlu
(To be published) Proceedings of the 40th International Symposium on Computer Architecture
HPCA '13 Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture
Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, and Onur Mutlu
Proceedings of the 19th International Symposium on High-Performance Computer Architecture
HPCA '13 MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems
Lavanya Subramanian, Vivek Seshadri, Yoongu Kim, Ben Jaiyen, and Onur Mutlu
Proceedings of the 19th International Symposium on High-Performance Computer Architecture
ISCA '12 A Case for Subarray-Level Parallelism (SALP) in DRAM (pdf | ppt)
Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, Onur Mutlu
Proceedings of the 39th International Symposium on Computer Architecture
IEEE Micro Top Picks '11 Thread Cluster Memory Scheduling (pdf)
Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter
IEEE Micro, Special Issue: Micro's Top Picks from 2010 Computer Architecture Conferences
MICRO '10 Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior (pdf | ppt)
Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter
Proceedings of the 43rd International Symposium on Microarchitecture
(Note: Algorithm 2 is revised compared to the published version of the paper.)
HPCA '10 ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers (pdf | ppt)
Yoongu Kim, Dongsu Han, Onur Mutlu, Mor Harchol-Balter
Proceedings of the 16th International Symposium on High-Performance Computer Architecture
One of four papers nominated for Best Paper.