N. Menezes, S. Pullela, A. Balivada and L.T. Pillage, “Skew Reduction in Clock Trees Using Wire Width Optimization”, Proceedings Custom Integrated Circuits Conference, May 1993.
http://users.ece.cmu.edu/~pileggi/wp-content/uploads/2020/05/CMU-logo-v4.png00awphttp://users.ece.cmu.edu/~pileggi/wp-content/uploads/2020/05/CMU-logo-v4.pngawp1993-05-01 08:00:002018-06-28 16:21:55Skew Reduction in Clock Trees Using Wire Width Optimization
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