U.S. Patent No. – High Performance Merge Sort with Scalable Parallelization and Full-Throughput Reduction – Sadi, Franchetti, Pileggi, October 27, 2021.
http://users.ece.cmu.edu/~pileggi/wp-content/uploads/2020/05/CMU-logo-v4.png00awphttp://users.ece.cmu.edu/~pileggi/wp-content/uploads/2020/05/CMU-logo-v4.pngawp2023-11-14 12:23:202023-11-14 12:23:20High Performance Merge Sort with Scalable Parallelization and Full-Throughput Reduction
