Delay Evaluation with Lumped Linear RLC Interconnect Circuit Models
L.T. Pillage and R.A. Rohrer, “Delay Evaluation with Lumped Linear RLC Interconnect Circuit Models”, Proceedings Decennial Caltech Conference on VLSI, March 1989.
A Quadratic Metric for the Initial Placement Problem with a Simple Solution Scheme
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpL.T. Pillage and R.A. Rohrer, “A Quadratic Metric for the Initial Placement Problem with a Simple Solution Scheme”, Proceedings Design Automation Conference, June 1988.
TALISMAN: A Piecewise Linear Circuit Simulator Based on Tree Link Analysis
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpL.T. Pillage, X. Huang and R.A. Rohrer, “TALISMAN: A Piecewise Linear Circuit Simulator Based on Tree Link Analysis”, Proceedings IEEE International Conference on Computer-Aided Design, November 1987.
Tree Link Partitioning for the Implicit Solution of Circuits
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpL.T. Pillage, X. Huang and R.A. Rohrer, “Tree Link Partitioning for the Implicit Solution of Circuits”, Proceedings IEEE International Symposium on Circuits and Systems, May 1987.
Contact
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pileggi@andrew.cmu.edu
Phone: 412-268-6774