Hierarchical Modeling of Electrostatic and Magnetostatic Coupling

S. Gupta and L. Pileggi, “Hierarchical Modeling of Electrostatic and Magnetostatic Coupling”, Proceedings of the SRC Techcon Conference, August 2003.

Simulation Approach for Inductance Effects of VLSI Interconnects

X. Qi, G. Leonhardt, D. Flees, X-D, Yang, S. Kim, S. Mueller, H. Mau and L. Pileggi, “Simulation Approach for Inductance Effects of VLSI Interconnects”, In Proc. of the Great Lakes Symposium on VLSI, May 2003.

Bounding the Efforts on Congestion Optimization for Physical Synthesis

D. Pandini, L. Pileggi, A. Strojwas, “Bounding the Efforts on Congestion Optimization for Physical Synthesis”, In Proc. of the Great Lakes Symposium on VLSI, May 2003.

Cheap and Under Control: The Next Implementation Fabric

I. Bolsens, A. Broom, C. Hamlin, P. Magarshack, Z. Or-Bach and L. Pileggi, Fast, “Cheap and Under Control: The Next Implementation Fabric”, IEEE/ACM Design Automation Conference, June 2003.

Exploring Regular Fabrics to Optimize the Performance-Cost Trade-Off

L. Pileggi, H. Schmit, A.J. Strojwas, et al, “Exploring Regular Fabrics to Optimize the Performance-Cost Trade-Off”, IEEE/ACM Design Automation Conference, June 2003.

Analog and RF Circuits Macromodels for System-Level Analysis

X. Li, P. Li, Y. Xu and L. Pileggi, “Analog and RF Circuits Macromodels for System-Level Analysis”, IEEE/ACM Design Automation Conference, June 2003.

NORM: Compact Model Order Reduction of Weakly Nonlinear Systems

P. Li and L. Pileggi, “NORM: Compact Model Order Reduction of Weakly Nonlinear Systems”, IEEE/ACM Design Automation Conference (Best Paper Award), June 2003.

An Architecture Exploration of Via Patterned Gate Arrays

C. Patel, A. Cozzie, H. Schmit and L. Pileggi, “An Architecture Exploration of Via Patterned Gate Arrays”, Internation Symposium on Physical Design, April 2003.

Power Comparison of Throughput Optimized IC Busses

E. Malley, A. Salinas, K. Ismail and L. Pileggi, “Power Comparison of Throughput Optimized IC Busses”, IEEE Symposium on VLSI, February 2003.

Heterogeneous Programmable Logic Block Architectures

A. Koorapaty, V. Chandra, K.Y. Tong, C. Patel, L. Pileggi and H. Schmit, “Heterogeneous Programmable Logic Block Architectures”, Design and Test in Europe Conference (DATE), March 2003.