Regular Fabrics for Nano-Scaled CMOS Technologies
L. Pileggi and A.J. Strojwas, “Regular Fabrics for Nano-Scaled CMOS Technologies”, International Solid State Circuits Conference (invited presentation), February 2006.
L. Pileggi and A.J. Strojwas, “Regular Fabrics for Nano-Scaled CMOS Technologies”, International Solid State Circuits Conference (invited presentation), February 2006.
X. Li, J. Le, L. Pileggi and A.J. Strojwas, “Projection-Based Performance Modeling for Inter/Intra-Die Variations”, Proceedings of the International Conference on Computer-Aided Design, November 2005.
X. Li, J. Le, M. Celik and L. Pileggi, “Defining Statistical Sensitivity for Timing Optimization of Logic Circuits with Large-Scale Process and Environmental Variations”, Proceedings of the International Conference on Computer-Aided Design, November 2005.
X. Li, P. Li and L. Pileggi, “Parameterized Interconnect Order Reduction with Explicit-and-Implicit Multi-Parameter Moment Matching for Inter/Intra-Die Variations”, Proceedings of the International Conference on Computer-Aided Design, November 2005.
X. Li, J. Wang, W. Chiang and L. Pileggi, “Performance-Centering Optimization for System-Level Analog Design Exploration”, Proceedings of the International Conference on Computer-Aided Design, November 2005.
P. Li, Y. Dong and L. Pileggi, “Temperature-Dependent Optimization of Cache Leakage Power Dissipation”, Proceedings of the International Conference on Computer Design, October 2005.
R. Batra, P. Li, L. Pileggi, W.J. Chiang, “A Behavioral Level Approach for Nonlinear Dynamic Modeling of Voltage-Controlled Oscillators”, Int’l Custom Integrated Circuits Conference, Sept. 2005.
G. Keskin, X. Li and L. Pileggi, “Reducing Power Supply Noise in Integrated Circuits Using Active Resistors”, Proceedings of the SRC Techcon Conference, October 2005.
P. Gopalakrishnan and L. Pileggi, “Timing Driven Initial Placement for FPGAs via Graph Matching”, Proceedings of the SRC Techcon Conference, October 2005.
Y. Xu, K. L. Hsiung, L. Pileggi, and S. Boyd, “OPERA: OPtimization with Ellipsoidal uncertainty for Robust Analog IC design”, Design Automation Conference, June 2005.

Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774
