Fixed Depth Reasoning in Satisfiability and its Applications to Combinatorial Optimization

B. Taylor, D. Morris and L. Pileggi, “Fixed Depth Reasoning in Satisfiability and its Applications to Combinatorial Optimization”, Proceedings of the SRC Techcon Conference, September 2009.

Economic Assessment of Lithography Strategies for the 22nm Technology Node

T. Jhaveri, A. J. Strojwas, L. Pileggi and V. Rovner, “Economic Assessment of Lithography Strategies for the 22nm Technology Node”, Proceedings of the SPIE/BACUS Symposium on Photomask Technology, September 2009.

SRAM Parametric Failure Analysis, Proceedings of ACM/IEEE Design Automation Conference

J. Wang, S. Yaldiz, X. Li and L. Pileggi, “SRAM Parametric Failure Analysis, Proceedings of ACM/IEEE Design Automation Conference”, June 2009.

Creating an Affordable 22nm Node using Design-Lithography Co-Optimization

A. J. Strojwas, T. Jhaveri, V. Rovner and L. Pileggi, “Creating an Affordable 22nm Node using Design-Lithography Co-Optimization”, Proceedings of ACM/IEEE Design Automation Conference, June 2009.

Efficient Statistical Analysis of Read Timing Failures in SRAM Circuits

S. Yaldiz, U. Arslan, X. Li and L. Pileggi, “Efficient Statistical Analysis of Read Timing Failures in SRAM Circuits”, IEEE Int’l Symposium on Quality in Electronic Design, March 2009.

Simplify to Survive: Prescriptive Layouts Ensure Profitable Scaling to 32nm and Beyond

Lars Liebmann, Larry Pileggi, Jason Hibbeler, Vyacheslav Rovner, Tejas Jhaveri, Greg Northrop, “Simplify to Survive: Prescriptive Layouts Ensure Profitable Scaling to 32nm and Beyond”, SPIE Advanced Lithography Conference, February 2009.

OPC Simplification & Mask Cost Reduction using Regular Design Fabrics

Tejas Jhaveri, Andrzej Strojwas, Larry Pileggi & Vyacheslav Rovner, “OPC Simplification & Mask Cost Reduction using Regular Design Fabrics”, SPIE Advanced Lithography Conference, February 2009.

Ring Oscillators for Single Process-Parameter Monitoring

Bin Wan, Jian Wang, Gokce Keskin, and Lawrence T. Pileggi, “Ring Oscillators for Single Process-Parameter Monitoring”, IEEE Workshop on Test Structure Design for Variability Characterization, November 2008.

A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS

J. Proesel and L. Pileggi, ‘A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS’, Int’l Custom Integrated Circuits Conference, Sept. 2008.

Variation-Tolerant SRAM Sense-Amplifier Timing Using Configurable Replica Bitlines

U. Arslan, M. McCartney, M. Bhargava, X. Li, K. Mai and L. Pileggi, “Variation-Tolerant SRAM Sense-Amplifier Timing Using Configurable Replica Bitlines”, Int’l Custom Integrated Circuits Conference, Sept. 2008.