A Wideband RF Receiver with >80 dB Harmonic Rejection Ratio

R. Liu, L. Pileggi and J. Weldon, “A Wideband RF Receiver with >80 dB Harmonic Rejection Ratio”, Int’l Custom Integrated Circuits Conference, September 2014.

Sub-20 nm Design Technology Co-Optimization for Standard Cell Logic

K. Vaidyanathan, L. Liebmann, A. Strojwas, L. Pileggi, “Sub-20 nm Design Technology Co-Optimization for Standard Cell Logic”, Int’l Conference on Computer-Aided Design, November 2014.

Integrating Emerging Devices and CMOS for Efficient Cellular Neural Networks

T. Jackson, V. Calayir and L. Pileggi, “Integrating Emerging Devices and CMOS for Efficient Cellular Neural Networks”, Proceedings of the SRC Techcon Conference, September 2014.

Efficient and Secure Intellectual Property (IP) Design with Split Fabrication

K. Vaidyanathan, R. Liu, E. Sumbul, Q. Zhu, F. Franchetti, L. Pileggi, “Efficient and Secure Intellectual Property (IP) Design with Split Fabrication”, Hardware-Oriented Security and Trust, May 2014.

Building Trusted ICs using Split Fabrication

K. Vaidyanathan, B. P. Das, E. Sumbul, R. Liu, L. Pileggi, “Building Trusted ICs using Split Fabrication”, Hardware-Oriented Security and Trust, May 2014.

Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack

K. Vaidyanathan, B. Prasad Das, L. Pileggi, “Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack”, IEEE/ACM Design Automation Conference, June 2014.

Fabrication Challenges in Developing All-Metal Magnetic Logic Circuits

M. T. Moneck, V. Sokalski, D. M. Bromberg, J. Wu, Z. Dai, L. Pileggi, J.-G. Zhu, “Fabrication Challenges in Developing All-Metal Magnetic Logic Circuits”, 2014 International Magnetics Conference.

mLogic: All Spin Logic Device and Circuits for Future Electronics

J.-G. Zhu, D. Bromberg, V. Sokalski, M.T. Moneck, J. Wu, Z. Dai, L. Pileggi, “mLogic: All Spin Logic Device and Circuits for Future Electronics”, IEEE Transactions on Magnetics, INTERMAG 2014.

A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI

V. H-C. Chen and L. Pileggi, “A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI”, International Solid State Circuits Conference (ISSCC), February 2014.

Toward Efficient Programming of Reconfigurable Radio Frequency (RF) Receivers

J. Tao, Y.-C. Wang, M. Jun, X. Li, R. Negi, T. Mukherjee, L. Pileggi, “Toward Efficient Programming of Reconfigurable Radio Frequency (RF) Receivers”, 19th Asia and South Pacific Design Automation Conference (ASP-DAC), January 2014.