Pre-characterization of ECL Gates for Timing Analysis
I. Tesu and L. Pileggi, “Pre-characterization of ECL Gates for Timing Analysis”, SCS ’95 International Symposium on Signals, Circuits & Systems, Iasi, Romania, October 1995.
Timing Analysis Models for Gates and Cells with Bipolar Transistor Output Stages
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpI. Tesu and L. Pileggi, “Timing Analysis Models for Gates and Cells with Bipolar Transistor Output Stages”, Proceedings of the IEEE ASIC Conference, 1995.
Transmission Line Synthesis
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpB. Krauter, R. Gupta, J. Willis and L. Pileggi, “Transmission Line Synthesis”, Proceedings of the Design Automation Conference , 1995.
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpN. Menezes, S. Pullela and L. Pileggi, “Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization”, Proceedings of the Design Automation Conference, 1995.
The Elmore Delay as a Bound for RC-Trees with Generalized Input Signals
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpR. Gupta, B. Krauter, B. Tutuianu, J. Willis and L. Pileggi, “The Elmore Delay as a Bound for RC-Trees with Generalized Input Signals”, Proceedings of the Design Automation Conference, 1995.
Constrained Multivariable Optimization of Transmission Lines with General Topologies
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpR. Gupta and L. Pileggi, “Constrained Multivariable Optimization of Transmission Lines with General Topologies”, Proceedings of the International Conference on Computer-Aided Design, 1995.
A Sequential Quadratic Programming Approach to Concurrent Gate and Wire Sizing
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpN. Menezes, R. Baldick and L. Pileggi, “A Sequential Quadratic Programming Approach to Concurrent Gate and Wire Sizing”, Proceedings of the International Conference on Computer-Aided Design, 1995.
Low Power IC Clock Tree Design
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpS. Pullela, N. Menezes and L.T. Pillage, “Low Power IC Clock Tree Design”, Proceedings Custom Integrated Circuits Conference, May 1995.
Sparse Partial Inductance Matrix Formulation
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpB. Krauter, D. Neikirk and L.T. Pillage, “Sparse Partial Inductance Matrix Formulation”, Progress in Electromagnetics Research Symposium, July 1995.
Wire Width Optimization of Transmission Lines for Low Power Design
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpRohini Gupta, John Willis and L.T. Pillage, “Wire Width Optimization of Transmission Lines for Low Power Design”, IEEE Multi-chip Module Conference, February 1995.
Contact
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774